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参数资料
| 型号： | RTC-62423B-0 |
| 厂商： | EPSON TOYOCOM CORP |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO24 |
| 封装： | SOP-24 |
| 文件页数： | 11/24页 |
| 文件大小： | 195K |
| 代理商： | RTC-62423B-0 |
RTC - 62421 / 62423
Page - 16
MQ152-05
4. Switch over between 24- and 12-hour clock modes
Switching between the 24- and 12-hour clock modes is done by writing 1 or 0 to the 24/12 bit and simultaneously performing a
RESET within the RTC. Since the 24/12 bit and the RESET bit are in the same control register F, follow the procedure below to set
them.
START
END
Reg.F
24/12
RESET
1
0 or 1
0**1B
←
Reg.F
24/12
RESET
0
0 or 1
0**0B
←
Set the CF register
Make sure that the value written to
the 24/12 bit at this poi nt is the same
as the previously written value.
5. Using the CS1 pin
The RTC-62421/RTC-62423 has 2 chip-select signal systems:
CS0
and CS1. Use
CS0
as chip-select for ordinary bus access.
CS1 is not only used for CPU bus control, it also has the main function of switching between standby mode and operating mode.
(1) Functions
Providing the CS1 pin with the rated voltage levels enables CS1 to have the following functions:
# Enabling interface with microprocessor during operation within the operating voltage range (5.0 V ±0.5 V)
# Reducing current consumption during standby (to prevent through currents caused by unstable inputs, which is inherent to
C-MOS devices)
# Protecting internal data during standby
To ensure these functions, make sure that operation of the CS1 pins observes that following conditions:
# Make sure that the voltage input to the CS1 pin during operation is at least 4/5 VDD.
# Make sure that the voltage input to the CS1 pin during standby is as close as possible to 0 V, to prevent through currents.
# Make sure that the operation conforms to the timing chart below during a shift to standby mode or a return to operating
mode.
*
Standby mode is a state in which a voltage lower than the RTC's rated range of operating supply voltage is applied (4.5 V
to 2.0 V). Under this condition, the timer continues to operate under battery back-up power, but the interface between the
interior and exterior of the RTC cannot be guaranteed.
(2) Timing
VIH2
(4/5VDD)
VIL2
(1/5VDD)
tCDR
2
sMin.
tR
2s Min.
4 V
VDD
CS1
Shift to standby mode
Data hold mode
Return to operation mode
Must be at least 2.0 V
Must be at no more than 1/5VDD
Do not access the RTC while the voltage at CS1 is changing
(3) Note
If the RTC is operated with timing conditions different from those shown above, data within the RTC could be overwritten during
a shift to standby mode or a return to operating mode. For example, if a write signal ( WR ) is generated during either of the
timing conditions (tCDR, tR) shown in the timing chart above, the data will be input before the RTC has stabilized. To ensure that
data is held throughout the entire standby process, make sure that the timing conditions shown in the chart are followed.
相关PDF资料 |
PDF描述 |
|---|---|
| RTC-72421A | 0 TIMER(S), REAL TIME CLOCK, PDIP18 |
| RTC-72421B | 0 TIMER(S), REAL TIME CLOCK, PDIP18 |
| RTC-72423A-0 | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| RTC-72423B-0 | REAL TIME CLOCK, PDSO24 |
| RTC-72423A-0 | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
相关代理商/技术参数 |
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