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参数资料
| 型号： | RTC-62423B-0 |
| 厂商： | EPSON TOYOCOM CORP |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO24 |
| 封装： | SOP-24 |
| 文件页数： | 5/24页 |
| 文件大小： | 195K |
| 代理商： | RTC-62423B-0 |
RTC - 62421 / 62423
Page - 10
MQ152-05
IRQ FLAG bit
*STD.P pin output
01
0
1
Interrupt generation (in synchronization
with count incrementation)
Writing of 0 to IRQ FLAG bit
The output levels of the STD.P pin are low (down) and open circuit (up).
Note:
If the STD.P pin output remains low as set, subsequently generated interrupts are ignored. In order to prevent
interrupts from being overlooked, write 0 to the IRQ FLAG bit before the next interrupt is generated, to return the
STD.P pin to high.
iii.
Initial setting of IRQ FLAG bit
If the interrupt mode is not used, set the IRQ FLAG bit to 1. If the interrupt mode is used, set the IRQ FLAG bit to 0.
(4) 30-second ADJ bit (D3)
The 30-seconds ADJ bit provides a 30-seconds correction (by which term is meant a rounding to the nearest whole minute) when 1
is written to it. The 30-seconds correction takes a maximum of 125
s to perform, and after the correction the 30-seconds ADJ
bit is automatically returned to 0. This operation also clears the sub-second bits of the internal counter down to the 1/8192-
seconds counter. During the 30-seconds correction, access to the counter registers at addresses 0 to C is inhibited, so monitor
the 30-seconds ADJ bit to check that this bit has returned to 0, before starting subsequent processing. If no access is made to
the RTC for 125
s or more after 1 is written to the 30-seconds ADJ bit, there is no need to check the 30-seconds ADJ bit again.
i.
Operation of 30-seconds ADJ bit
Writing 1 to the 30-seconds ADJ bit performs a 30-second correction. This 30-seconds correction changes the seconds and
minutes digits as shown below. If the minutes digits have been incremented, an upward carry is propagated.
Status of seconds digits before correction
Status of seconds digits after correction
Up to 29 seconds
00 seconds. No carry to the minutes digits.
30 to 59 seconds
00 seconds. Carry to the minutes digits.
Example: The correction caused by the 30-seconds ADJ bit sets the time within the RTC to 00:00:00 if it was within the range
of 00:00:00 to 00:00:29, or to 00:01:00 if it was within the range of 00:00:30 to 00:00:59.
ii.
Access inhibited after 30-seconds correction
For 125
s after 1 is written to the 30-seconds ADJ bit, the RTC is engaged in internal processing, so read to and write from
the S1 to W registers is inhibited. The 30-seconds ADJ bit is automatically cleared to 0 at the end of the 125
s.
3. CE register (control register E)
(1) MASK bit (D0)
The MASK bit controls the STD.P pin output. The relationships between the MASK bit, ITRPT/STND bit, and STD.P pin output are
as follows:
MASK
ITRPT/STND
Status of STD.P pin output
0
Fixed-period pulse output mode
0
1
Interrupt mode
1
0 or 1
Open circuit (while the MASK bit remains at 1)
The timings of the MASK bit, ITRPT/STND bit, and STD.P pin output are as follows:
1.
Fixed-period pulse output mode (ITRPT/STND = 0)
IRQ FLAG bit
*STD.P pin
Nothing is output
because the MASK
bit is at 1
01
0
1
0
01
0
1
0
MASK bit
Output timing
Automatic return
The output levels of the STD.P pin are low (down) and open circuit (up).
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| RTC-72421A | 0 TIMER(S), REAL TIME CLOCK, PDIP18 |
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| RTC-72423B-0 | REAL TIME CLOCK, PDSO24 |
| RTC-72423A-0 | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
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