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参数资料
| 型号： | RTC-7301SFB |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO24 |
| 封装： | SSOP-24 |
| 文件页数： | 2/28页 |
| 文件大小： | 274K |
| 代理商： | RTC-7301SFB |
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RTC - 7301 SF / DG
Page - 7
MQ332-05
6. Registers
6-1. Register table
Bank 0
Clock and calendar registers
Bank 1
Alarms and FOUT registers
Address
Register
bit 3
bit 2
bit 1
bit 0
Address
Register
bit 3
bit 2
bit 1
bit 0
0
1 second
8
4
2
1
0
1 second
8
4
2
1
10 second
Fos
40
20
10
1
10 second
AE
40
20
10
2
1 minute
8
4
2
1
2
1 minute
8
4
2
1
3
10 minute
!
40
20
10
3
10 minute
AE
40
20
10
4
1 hour
8
4
2
1
4
1 hour
8
4
2
1
5
10 hour
!
20
10
5
10 hour
AE
20
10
6
Day
!
4
2
1
6
Day
AE
4
2
1
7
1 day
8
4
2
1
7
1 day
8
4
2
1
8
10 day
!
20
10
8
10 day
AE
20
10
9
1 month
8
4
2
1
9
-
A
10 month
!
10
A
-
B
1 year
8
4
2
1
B
CS1
Controller
CTEMP CDT_ON
C
10 year
80
40
20
10
C
FOUT divider
ratio setting
register
!
FD2
FD1
FD0
D
100 year
800
400
200
100
D
FOUT divider
ratio setting
register
FE
!
FD4
FD3
E
1000 year
1,2
TEST
1,2
TEMP
2000
1000
E
Alarm control
1,2
TEST
1,2
TEMP
AF
AIE
1
F
1
Control
register
1
Bank
Sel 1
1
Bank
Sel 0
1
STOP
1
BUSY
/ ADJ
1
F
1
Control
register
1
Bank
Sel 1
1
Bank
Sel 0
1
STOP
1
BUSY
/ ADJ
Bank 2
Digital offset and timer registers
Address
Registers
bit 3
Bit 2
bit 1
bit 0
0
DT3
DT2
DT1
DT0
1
Digital offset
DT_ON
DT6
DT5
DT4
2
!
3
!
4
8
4
2
1
5
Timer counter
preset value
128
64
32
16
6
8
4
2
1
7
Timer counter
data
128
64
32
16
8
Timer settings
TE
TI / TP
TD1
TD0
9
!
A
!
B
!
C
!
D
!
E
Timer control
1,2
TEST
1,2
TEMP
TF
TIE
1
F
1
Control
register
1
Bank
Sel 1
1
Bank
Sel 0
1
STOP
1
BUSY
/ ADJ
FOUT setting registers ( Bank 1 Registers C and D )
Timer setting registers ( Bank 2 Register 8 )
FD4
FD3
Source clock
FD2
FD1
FD0
Divider
ratio
TD1
TD0
Source clock
0
32768 Hz
0
1 /
1
0
4096 Hz
0
1
1024 Hz
0
1
1 /
2
0
1
64 Hz
1
0
32 Hz
0
1
0
1 /
3
1
0
Update in seconds
1
1 Hz
0
1
1 /
6
1
Update in minutes
1
0
1 /
5
1
0
1
1 / 10
1
0
1 / 15
1
1 / 30
1) [*1] bits (all bits of the control registers and the TEST bits and
TEMP bits) are common for all BANKs.
2) When the power is turned on initially, the [*2] TEST and TEMP bits
are cleared to 0.
Also, Fos is set to 1, but because other the
register values of other bits are unknown, always make their initial
settings.
When doing so, do not make settings for date and time
that are impossible.
We do not guarantee proper operation of the
clock for such settings.
3) The TEST bit is our internal test bit.
Always use with this set to "0."
Note) When using the RTC-7301DG, always use with the [*2] TEST
and TEMP bits set to “0.”
4) Write is possible for the AF and TF bits only when set to “0.”
5) " ! " bits should be used when set to “0” after the initial settings.
6) "
" bits can be used as RAM.
7) When not using the alarm interrupt, it is possible to use BANK 1
registers 0 to 8 as RAM.
(Total 36 bits)
8) When not using the timer interrupt, it is possible to use BANK 2
registers 4 to 5 as RAM.
(Total 8 bits)
9) When not using digital pace adjustment, Bank 2 registers 0 to 1 can
be used as RAM.
(Total 7 bits)
10) The BUSY/ADJ bit is busy when reading and is a 30 second ADJ bit when
writing.
Also, a BUSY flag is set 122
s before and after the time update
timing.
The ADJ bit is cleared to 0 automatically at a maximum of 244
s after being set.
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