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参数资料
| 型号： | RTC-7301SFB |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO24 |
| 封装： | SSOP-24 |
| 文件页数： | 8/28页 |
| 文件大小： | 274K |
| 代理商： | RTC-7301SFB |
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RTC - 7301 SF / DG
Page - 13
MQ332-05
6-2-7. Control registers (Common to each Bank Reg-E and Reg-F )
Address
bit 3
Bit 2
bit 1
bit 0
E
TEST
TEMP
F
Bank Sel 1
Bank Sel 0
STOP
BUSY/ADJ
TEST bit: This bit is for our internal testing.
Note) The TEST bit is for our internal testing, so always set to [ TEST bit –“0” ].
Be careful not to mistakenly write a “1” when writing data to other bits of the same register.
TEMP bit
When this bit is set to “1”, the VTEMP pin outputs the temperature sensor voltage (analog).
When it is set to “0,” the VTEMP pin is set to a high impedance.
This bit is reset to “0” when the power is turned
ON.
Note) Because the VTEMP pin is not set on the RTC-7301DG, always set to [ TEMP bit = “0” ].
When using with [ TEMP bit = “1” ], power current consumption will increase.
Bank Sel bit
This bit specifies the Bank to access (read/write)
Bank Sel 1
Bank Sel 0
Access bank name
0
Bank0
0
1
Bank1
1
0
Bank2
1
Bank1
STOP bit
When this bit is set to “1”, the timekeeper is set to STOP and RESET from the 32 Hz divider counter.
This is used when setting the clock data.
The timekeeper starts when it is “0.”
When setting the date and time data, wait a minimum of 122
s after writing “1” to this bit, then set the date and
time data.
BUSY/ADJ bit
This bit is in BUSY mode when reading and in ADJ mode when writing. The data"1" can't set to this bit.
When “1” is written to this bit, the following operations will be performed between a minimum of 61
s to a
maximum of 183
s.
When the seconds display is 00 to 29 Resets the counter up to 32 Hz for the seconds and sets the second
digits to 00 seconds.
When the seconds display is 30 to 59 Resets the counter up to 32 Hz for the seconds and sets the second
digits to 00 seconds and adds one minute to the minute digit.
Later, this bit is automatically reset to “0” after
244
s (Max.)
Because when BUSY = 1, the counter is updated, read out to the clock and calendar when BUSY = 1.
If BUSY=0,
it reads out stable data without updating the time at a maximum of 122
s.
There is a possibility that unstable data will be read out while updating the clock if reading out when BUSY=1.
The following will occur when BUSY=1.
1 ) Normal 1 second digit raise is processed.
2 ) Processing of the
±30 second adjust (When writing 1 to the ADJ bit.)
Function operation table
Bit
Function
STOP
ADJ
Clock
Timer
Alarm
FOUT
0
Runs
*1
Runs
*1
0
1
30 adjust.
Runs
*1
Runs
*1
1
0
Stops
*1
Stops
*2
1
Stops&30 adjust.
*1
Stops
*2
1 : When source clock set to 1Hz or 1 minute, in a timing of digital adjustment or 30ADJ, a period of a timer and a period of
FOUT change a little.
When STOP-Bit is "1", operation is stops.
2 : When source clock is 1Hz,The output is halt.
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相关代理商/技术参数 |
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| RTC-840 | 制造商:AAEON 制造商全称:AAEON 功能描述:Intel?? Corea?￠ Duo U2500 1.2 GHz Processor |
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| RTC-8563SA | 制造商:EPSONTOYOCOM 制造商全称:Epson ToYoCom 功能描述:RTC-8563SA |
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| RTC-8564JE | 制造商:Epson Toyocom Corporation 功能描述:32.768kHz 275nA@3ViTyp.j 3.0V (typ.) 7.0~5.4~1.5mm +85 -40 5}23ppm@+25/3.0V 7mm 5.4mm 1.5mm 制造商:Epson Toyocom Corporation 功能描述:RTC I2C BUS INTERFACE SMD VSOJ-20 制造商:Epson Toyocom Corporation 功能描述:RTC I2C BUS INTERFACE, SMD, VSOJ-20 制造商:Epson Toyocom Corporation 功能描述:IC, RTC, FULL CALENDAR, VSOJ-20; Clock Format:12Hr / 24Hr; Clock IC Type:RTC; Supply Voltage Min:1.8V; Supply Voltage Max:5.5V; Digital IC Case Style:VSOJ; No. of Pins:20; IC Interface Type:I2C; Operating Temperature Min:-40C ;RoHS Compliant: Yes 制造商:Epson Toyocom 功能描述:RTC module,I2C Bus,Alarm,timer func |
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