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参数资料
| 型号： | RTC-7301SFB |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDSO24 |
| 封装： | SSOP-24 |
| 文件页数： | 6/28页 |
| 文件大小： | 274K |
| 代理商： | RTC-7301SFB |
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RTC - 7301 SF / DG
Page - 11
MQ332-05
TF bit: ( Timer Flag )
The TF bit set to 1 when the timer reaches zero. The data is maintained until 0 is written. It is not possible to write 1.
TE bit: ( Timer Enable )
When TE is set to 1 , timer is running.
When TE is cleared to 0, Timer stops.
TIE bit: ( Timer Interrupt Enable )
This bit determines whether or not to drive the /IRQ pin when there has been a timer interrupt.
When the TIE bit is “0,” the timer interrupt is not output to the /IRQ pin.
TI/TP bits: ( Interrupt Signal Output Mode Select. Interrupt / Periodic )
These bits set the output mode of the timer interrupt signal.
TI/TP
0
1
Function
Level interrupt mode
The /IRQ pin is “L” immediately upon the
occurrence of the timer interrupt (however,
when TIE = 1) and the TF bit is “1” and the
/IRQ is maintained at “L” until “0” is written to
the TF bit.
Repeat interrupt mode (interval)
The /IRQ pin is “L” immediately upon the occurrence
of the timer interrupt (however, when TIE = 1) and
the TF bit is “1.”
Subsequently, the /IRQ pin enters high impedance
and the TF bit is “1” is retained until “0” is written.
Alarm-interrupt and a both signal of a timer-interrupt output it from /IRQ terminal.
Even if the output of one interrupt is prohibition state, another interrupt occur and /IRQ terminal becomes LOW
active if it is a state of the output permission.
If the hardware interrupt is not being used, clear both the TIE and AIE bits to “0” and monitor both flag bits of AF
and TF with the software, if necessary.
Timer operation when the TI/TP bit is “0” is that the timer count register counts down and when the data reaches
zero, the TE bit is cleared and the counter automatically stops.
The value of the timer count register when the
timer automatically stops is zero.
Timer operation when the TI/TP bit is “1” is that the timer counter register counts down and when the data reaches
zero, the timer counter register data is reloaded and count down begins again.
This can be used as the interval
timer (repeat mode).
Reg-6 and 7 are read only, and can read the current value of the 8 bit pre-settable down counter. It cannot write
the data.
The pre-settable binary down-counter is updated when data is written to the Reg-4 and 5 registers. Data written
to the Reg-4 and 5 registers is retained until it is written again.
A timer interrupt does not occur from the /IRQ pin even if the data when the timer counter (Reg-4 and 5) reaches
zero is set when the TE bit is “1.”
There is an error in time of 0 to 1 cycles of the selected source clock with 1 timer operation.
Also, if the timer operation time is less than 1 cycle of the source clock, the count will may not be performed
normally.
Particularly, be aware that, when using minute update clock from clock register, for the source clock, there will be
an error of a maximum of 60 seconds depending on the timing.
The timer starts counting down from the edge of the rise of /WR corresponding to the TE bit in the time chart
below, in the data write mode.
When the TE bit is “0,” the counter stops. When the TE bit is “1”, the count starts.
Using this function enables you to stop the counter part-way through timer operations, but when the timer starts,
be aware that an error will occur at the maximum of the source clock period.
For example, when source clock set to 1 minute.Timer does countdown and stops from TE=0 after 1 minute
(maximum), and there is the case that interrupt occurs.
When interrupt is unnecessary, set TIE bits adequately, and prohibit unprepared interrupt.
Timer source clock
Write timing of the TE bit.
0 to 1
or
1 to 0.
Error
By TE=0
→ 1
TE=1 validates it from this timing,
the first countdown occurs with
negative edge of the next clock.
( TE = 1
→ 0 ( timer stops )
Timer does the last countdown by this
timing and stops.
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