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参数资料
| 型号： | S1R72C05B10 |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA121 |
| 封装： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TFBGA-121 |
| 文件页数： | 4/49页 |
| 文件大小： | 545K |
| 代理商： | S1R72C05B10 |
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4. FUNCTIONS
S1R72C05*** Data Sheet (Rev.1.00)
EPSON
7
4.6 CPU-I/F
This LSI is connected to the CPU via a 16-bit interface. Endian settings can be set as Big Endian or Little
Endian in 16-bit steps. For Big Endian, registers with even addresses can be accessed above the bus (CD[15:8]),
while registers with odd addresses can be accessed below the bus (CD[7:0]). For Little Endian, registers with
even addresses can be accessed below the bus (CD[7:0]), while registers with odd addresses can be accessed
above the bus (CD[15:8]).
The bus mode can be set to either Strobe mode for accessing using high/low strobe (XWRH/XWRL) or Byte
Enable mode for accessing using high/low byte enable (XBEH/XBEL) for writing in 8-bit. Endian and bus
mode are set by the CPUIF_MODE register immediately after resetting.
The CPU-I/F on this LSI includes 2-ch DMA (slave).
The registers that are accessible will depend on the power management state. For detailed information, refer
to the LSI Technical Manual.
4.7 IDE-I/F
This LSI includes an IDE host function supporting ATA/ATAPI6, which supports PIO modes 0 to 4, Multi
Word DMA, and UDMA modes 0 to 5 transfer modes.
4.8 USB Device I/F
This LSI supports high-speed specification USB device functions that comply with USB 2.0 (Universal Serial
Bus Specification Revision 2.0) standards.
4.8.1 Speed Mode and Transfer Type
This LSI supports HS (480 Mbps) and FS (12 Mbps) speed modes when operating USB devices. The speed
mode is automatically set by the speed negotiations performed when the bus is reset. For example, HS transfer
mode will be selected automatically by speed negotiations if connected to a USB host that supports HS speed
mode. (Note that FS speed mode can be set deliberately via register settings.)
All transfer types stipulated in the USB 2.0 standard are supported, including control transfer (endpoint 0),
bulk, interrupt, and isochronous transfers.
4.8.2 Resources
4.8.2.1 Endpoint
This LSI includes endpoint 0 and five standard endpoints. Endpoint 0 supports control transfer. The standard
endpoints support bulk, interrupt, and isochronous transfers. The standard endpoint numbers, maximum packet
size, and transfer direction (IN/OUT) can be set as desired.
4.8.2.2 FIFO
This LSI includes 4.5 kB of FIFO for use with USB data transfer. This forms the data transfer route with USB.
The FIFO capacity for each endpoint can be assigned as desired through software. For example, performance
can be improved by assigning an adequate FIFO area to the endpoints for bulk transfers.
4.8.3 Data Flow
Endpoints are assigned to USB FIFO areas on a one-to-one basis. Responses are returned to USB transactions
automatically, depending on the USB FIFO effective free capacity (for OUT transfer) or effective data quantity
(for IN transfer). Thus, the software need not be directly involved in individual transactions, allowing USB data
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相关代理商/技术参数 |
参数描述 |
|---|---|
| S1R72U01 | 制造商:EPSON 制造商全称:EPSON 功能描述:Ease of use and easy connections (serial connections) |
| S1R72U06 | 制造商:EPSON 制造商全称:EPSON 功能描述:Ease of use and easy connections (serial connections) |
| S1R72U06F12E100 | 制造商:Epson Electronics America Inc 功能描述:USB FS Host controller with embedded HID and Mass Storage class |
| S1R72U06F12E2 | 功能描述:USB 接口集成电路 USB FS Host Ctrlr w/ HID Mass storage RoHS:否 制造商:Cypress Semiconductor 产品:USB 2.0 数据速率: 接口类型:SPI 工作电源电压:3.15 V to 3.45 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:WLCSP-20 |
| S1R72U16 | 制造商:EPSON 制造商全称:EPSON 功能描述:Allows USB devices to be controlled as IDE devices |
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