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| 型号： | S1R72V18B10 |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA121 |
| 封装： | PLASTIC, FBGA-121 |
| 文件页数： | 37/37页 |
| 文件大小： | 365K |
| 代理商： | S1R72V18B10 |
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4. Explanation of Functions
4
EPSON
S1R72V18 Data Sheet (Rev. 1.00)
4. Explanation of Functions
For details of the register names used in the following discussion, refer to the Technical Manual for this LSI.
Apart from USB device functions, some of the registers in this LSI have the same functions for each port.
Note that this is indicated only when explaining the functions for individual ports.
4.1
Power Supply
This LSI has three power supply systems and a common GND. The power supply systems consist of
HVDD (3.3 V) for the USB I/O power supply, CVDD (3.3 V to 1.8 V) for the CPU I/F power supply,
and LVDD (1.8 V) for internal circuits and TEST I/O. (See Figure 4-1.)
I
O
CPU
-I/F
FIFO
SIE_0
MTM_0
CPU
USB
LVDD
HVDD
CVDD
1.8V to 3.3V
1.8V
3.3V
TEST
IO
SIE_1
MTM_1
Figure 4-1
S1R72V18 power supply circuit diagram
The sequence of steps for turning the power supplies on and off are described below.
This LSI does not allow individual power supply circuits to be held in a continuous on or off state.
Also, the following restrictions apply to the sequence for turning the CVDD/HVDD I/O power
supplies and LVDD internal power supply on or off. There are no restrictions on the sequence for
turning the CVDD and HVDD power supplies on or off.
In the power on sequence, the LVDD must be turned on before turning on the CVDD and HVDD.
In the powering off sequence, the CVDD and HVDD must be turned off before turning off the
LVDD.
If power supply circuit characteristics or the power supply load make this sequence impossible to
follow, the CVDD or HVDD must not be on for more than 1 second while the LVDD is off.
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