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| 型号： | S1R72V18B10 |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA121 |
| 封装： | PLASTIC, FBGA-121 |
| 文件页数： | 5/37页 |
| 文件大小： | 365K |
| 代理商： | S1R72V18B10 |
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4. Explanation of Functions
8
EPSON
S1R72V18 Data Sheet (Rev. 1.00)
4.6.2.2
FIFO
The LSI ports include 4.5 kB of FIFO for use with USB data transfers. This
forms the data transfer route with USB. The FIFO capacity of each endpoint
can be assigned as desired by the software. For example, performance can be
improved by assigning a sufficient size FIFO area to the endpoints for bulk
transfers.
4.6.3
Data Flow
Endpoints are assigned to USB FIFO areas on a one-to-one basis, and responses are
returned to USB transactions automatically, depending on effective USB FIFO free
capacity (for OUT transfers) or effective data quantity (for IN transfers). This means the
software does not need to be directly involved in individual transactions, allowing USB
data transfers to be controlled as data flows at the USB FIFO.
USB FIFO
Endpoint
USB Host
IN token
Data quantity <
MaxPktSize
NAK handshake
IN token
Data quantity >=
MaxPktSize
DATA packet
ACK handshake
CPU
Write
FIFO_Empty
Write
IN token
Data quantity <
MaxPktSize
Write
Read
IN transaction
(NAK response)
IN transaction
(Data reply)
IN transaction
(NAK response)
Transfer sent
NAK handshake
FIFO_Full
IN token
Data quantity >=
MaxPktSize
DATA packet
ACK handshake
IN transaction
(Data reply)
Empty
Data
Figure 4-4
Typical data flow (with FIFO assigned for MaxPktSize and IN transfer)
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