- 您现在的位置：买卖IC网 > PDF目录98069 > S1R72V18B10 UNIVERSAL SERIAL BUS CONTROLLER, PBGA121 PDF资料下载
参数资料
| 型号： | S1R72V18B10 |
| 元件分类： | 总线控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PBGA121 |
| 封装： | PLASTIC, FBGA-121 |
| 文件页数： | 4/37页 |
| 文件大小： | 365K |
| 代理商： | S1R72V18B10 |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页
4. Explanation of Functions
S1R72V18 Data Sheet (Rev. 1.00)
EPSON
7
4.5
CPU-I/F
This LSI is connected to the CPU via a 16-bit interface. Endian settings can be set as Big Endian or
Little Endian in 16-bit steps. For Big Endian, registers with even addresses can be accessed above the
bus (CD[15:8]), while registers with odd addresses can be accessed below the bus (CD[7:0]). For
Little Endian, registers with even addresses can be accessed below the bus (CD[7:0]), while registers
with odd addresses can be accessed above the bus (CD[15:8]).
The bus mode can be set to either Strobe mode for access using high/low strobe (XWRH/XWRL) or
Byte Enable mode for access using high/low byte enable (XBEH/XBEL) for writing the first or last 8
bits. Endian and bus mode is set by the CPUIF_MODE register immediately after reset cancelling.
The CPU-I/F on this LSI includes 1-ch DMA (slave) for each port (2-ch in total).
The registers that can be accessed will depend on the power management state. For details, refer to
the LSI Technical Manual.
4.6
USB Device I/F
This LSI supports High-Speed specification USB device functions complying with the USB 2.0
(Universal Serial Bus Specification Revision 2.0) standards.
4.6.1
Speed Mode and Transfer Type
This LSI’s USB device function supports HS (480 Mbps) and FS (12 Mbps) speed modes.
The speed mode is set automatically by the speed negotiation performed when resetting the
bus. For example, HS transfer mode is selected automatically by speed negotiation if
connected to a USB host that supports HS speed mode. In addition, the register can be set
so that FS speed mode is always selected in speed negotiations.
All transfer types stipulated under the USB 2.0 standard are supported, including control
transfers (endpoint 0), bulk transfers, interrupt transfers, and isochronous transfers.
4.6.2
Resources
4.6.2.1
Endpoint
This LSI’s USB device function includes endpoint 0 and five standard
endpoints. Endpoint 0 supports control transfers. The standard endpoints
support bulk transfers, interrupt transfers, and isochronous transfers. The
standard endpoint numbers, maximum packet size, and transfer direction
(in/out) can be set as desired.
相关PDF资料 |
PDF描述 |
|---|---|
| S1R72V27B05 | UNIVERSAL SERIAL BUS CONTROLLER, PBGA60 |
| S2024B-8 | 32-BIT, DSP-CROSSBAR SWITCH, PQFP196 |
| S2025A | 32-BIT, DSP-CROSSBAR SWITCH, PQFP196 |
| S2025C-15 | 32-BIT, DSP-CROSSBAR SWITCH, PQFP196 |
| S2028A | 32-BIT, DSP-CROSSBAR SWITCH, PQFP224 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| S1R72V27 | 制造商:EPSON 制造商全称:EPSON 功能描述:Built-in pull-down resistor for downstream ports (no external circuit required) |
| S1R77081F | 制造商:EPSON 制造商全称:EPSON 功能描述:RSDS Transmitter/Receiver |
| S1R8ADMTBK | 制造商:Hubbell Wiring Device-Kellems 功能描述:S1R FRPT 8 ABANDONMENT PLATE |
| S1R8CSPA | 制造商:Hubbell Wiring Device-Kellems 功能描述:S1R FRPT 8SP C1 2X EXTRON AAP UNITS |
| S1R8CSPB | 制造商:Hubbell Wiring Device-Kellems 功能描述:S1R FRPT 8SP C1 BLANK |
发布紧急采购，3分钟左右您将得到回复。