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参数资料
| 型号： | S29CL032J0JFFM020 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 1M X 32 FLASH 3.3V PROM, 54 ns, PBGA80 |
| 封装： | 13 X 11 MM, 1 MM PITCH, LEAD FREE, FORTIFIED, BGA-80 |
| 文件页数： | 66/79页 |
| 文件大小： | 2994K |
| 代理商： | S29CL032J0JFFM020 |
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March 30, 2009 S29CD-J_CL-J_00_B3
S29CD-J & S29CL-J Flash Family
69
Data
She e t
18.8
Erase and Programming Performance
Notes
1. Typical program and erase times assume the following conditions: 25
°C, 2.5 V V
CC, 100K cycles. Additionally, programming typicals assume checkerboard
pattern.
2. Under worst case conditions of 145°C, VCC = 2.5 V, 1M cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 20.1 and Table 20.2 for further
information on command definitions.
6. PPBs have a program/erase cycle endurance of 100 cycles.
7. Guaranteed cycles per sector is 100K minimum.
18.9
PQFP and Fortified BGA Pin Capacitance
Notes
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Table 18.7 Erase and Programming Performance
Parameter
Typ
Max
Unit
Comments
Sector Erase Time
0.5
5
s
Excludes 00h programming prior to erasure
Chip Erase Time
16 Mb = 23
32 Mb = 46
16 Mb = 230
32 Mb = 460
s
Double Word Program Time
8
130
s
Excludes system level overhead (Note 5)
Accelerated Double Word Program Time
8
130
s
Accelerated Chip Program Time
16 Mb = 5
32 Mb = 10
16 Mb = 50
32 Mb = 100
s
Chip Program Time, x32 (Note 3)
16 Mb = 12
32 Mb = 24
16 Mb = 120
32 Mb = 240
s
Table 18.8 PQFP and Fortified BGA Pin Capacitance
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
6
7.5
pF
COUT
Output Capacitance
VOUT = 0
8.5
12
pF
CIN2
Control Pin Capacitance
VIN = 0
7.5
9
pF
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