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| 型号： | S29WS256N0PBAW010 |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| 中文描述： | 16M X 16 FLASH 1.8V PROM, 70 ns, PBGA84 |
| 封装： | 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84 |
| 文件页数： | 14/95页 |
| 文件大小： | 1745K |
| 代理商： | S29WS256N0PBAW010 |
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October 29, 2004 S29WSxxxN_00_F0
21
Pre l i m i n a r y
The device outputs subsequent words tBACC after the active edge of each successive clock cy-
cle, which also increments the internal address counter. The device outputs burst data at this
rate subject to the following operational conditions:
starting address: whether the address is divisible by four (where A[1:0] is 00). A divisi-
ble-by-four address incurs the least number of additional wait states that occur after the
initial word. The number of additional wait states required increases for burst operations
in which the starting address is one, two, or three locations above the divisible-by-four
address (i.e., where A[1:0] is 01, 10, or 11).
boundary crossing: a physical aspect of the device that exists every 128 words, starting
at address 00007Fh. Higher operational speeds require one additional wait state. Refer to
Tables 7.10–7.13 for details. Figure 11.20 shows the effects of boundary crossings at
higher frequencies.
clock frequency: the speed at which the device is expected to burst data. Higher speeds
show the effects of frequency on burst operation.
In all cases, with or without latency, the RDY output indicates when the next data is available
to be read.
Table 7.5 shows the latency that occurs in the S29WS256N device when (x indicates the rec-
ommended number of wait states for various operating frequencies, as shown in Table 7.15,
configuration register bits CR13-CR11).
frequency, and wait state setting (configuration register bits CR13–CR11) for the S29WS128N
and S29WS064N devices. Tables 7.10–7.13 includes the wait state that occurs when crossing
the internal boundary.
Table 7.5. Address Latency for x Wait States (
≤ 80 MHz, WS256N only)
Table 7.6. Address Latency for 6 Wait States (
≤ 80 MHz)
Table 7.7. Address Latency for 5 Wait States (
≤ 68 MHz)
Word
Wait States
Cycle
0
x ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
x ws
D1
D2
D3
1 ws
D4
D5
D6
D7
D8
2
x ws
D2
D3
1 ws
D4
D5
D6
D7
D8
3
x ws
D3
1 ws
D4
D5
D6
D7
D8
Word
Wait States
Cycle
0
6 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
6 ws
D1
D2
D3
1 ws
D4
D5
D6
D7
D8
2
6 ws
D2
D3
1 ws
D4
D5
D6
D7
D8
3
6 ws
D3
1 ws
D4
D5
D6
D7
D8
Word
Wait States
Cycle
0
5 ws
D0
D1
D2
D3
D4
D5
D6
D7
D8
1
5 ws
D1
D2
D3
D4
D5
D6
D7
D8
D9
2
5 ws
D2
D3
1 ws
D4
D5
D6
D7
D8
D9
3
5 ws
D3
1 ws
D4
D5
D6
D7
D8
D9
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相关代理商/技术参数 |
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| S29WS256N0PBAW011 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| S29WS256N0PBAW012 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS256N0PBAW013 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 Megabit (16/8/4 M x 16-Bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst Mode Flash Memory |
| S29WS256N0PBAW110 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
| S29WS256N0PBAW111 | 制造商:SPANSION 制造商全称:SPANSION 功能描述:256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY |
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