参数资料
型号: S29WS256N0PBAW010
厂商: SPANSION LLC
元件分类: PROM
英文描述: 256/128/64 MEGABIT CMOS 1.8 VOLT ONLY SIMULTANEOUS READ/WRITE BURST MODE FLASH MEMORY
中文描述: 16M X 16 FLASH 1.8V PROM, 70 ns, PBGA84
封装: 11.60 X 8 MM, LEAD FREE, PLASTIC, FBGA-84
文件页数: 17/95页
文件大小: 1745K
代理商: S29WS256N0PBAW010
24
S29WSxxxN_00_F0 October 29, 2004
Pr e l i m i n a r y
7.3.2
8-, 16-, 32-Word Linear Burst Read with Wrap Around
In a linear burst read operation, a fixed number of words (8, 16, or 32 words) are read from
consecutive addresses that are determined by the group within which the starting address
falls. The groups are sized according to the number of words read in a single burst sequence
for a given mode (see Table 7.14).
For example, if the starting address in the 8-word mode is 3Ch, the address range to be read
would be 38-3Fh, and the burst sequence would be 3C-3D-3E-3F-38-39-3A-3Bh. Thus, the
device outputs all words in that burst address group until all word are read, regardless of
where the starting address occurs in the address group, and then terminates the burst read.
In a similar fashion, the 16-word and 32-word Linear Wrap modes begin their burst sequence
on the starting address written to the device, then wrap back to the first address in the se-
lected address group.
Note that in this mode the address pointer does not cross the boundary that occurs every 128
words; thus, no wait states are inserted (except during the initial access).
Table 7.14. Burst Address Groups
7.3.3
8-, 16-, 32-Word Linear Burst without Wrap Around
If wrap around is not enabled for linear burst read operations, the 8-word, 16-word, or 32-
word burst will execute up to the maximum memory address of the selected number of words.
The burst will stop after 8, 16, or 32 addresses and will not wrap around to the first address
of the selected group.
For example, if the starting address in the 8- word mode is 3Ch, the address range to be read
would be 39-40h, and the burst sequence would be 3C-3D-3E-3F-40-41-42-43h if wrap
around is not enabled. The next address to be read will require a new address and AVD#
pulse. Note that in this burst read mode, the address pointer may cross the boundary that
occurs every 128 words.
7.3.4 Configuration Register
The configuration register sets various operational features, most of which are associated
with burst mode. Upon power-up or hardware reset, the device defaults to the asynchronous
read mode, and the configuration register settings are in their default state. The host system
should determine the proper settings for the entire configuration register, and then execute
the Set Configuration Register command sequence, before attempting burst operations. The
configuration register is not reset after deasserting CE#. The Configuration Register can also
be read using a command sequence (see Table 12.1). The following list describes the register
settings.
Mode
Group Size
Group Address Ranges
8-word
8 words
0-7h, 8-Fh, 10-17h,...
16-word
16 words
0-Fh, 10-1Fh, 20-2Fh,...
32-word
32 words
00-1Fh, 20-3Fh, 40-5Fh,...
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