TIMER 1
S3C825A/P825A
11-2
Timer 1 Control Register (TACON)
You use the timer 1 control register, TACON, to
— Enable the timer 1 operating (interval timer)
— Select the timer 1 input clock frequency
— Clear the timer 1 counter, TACNT and TBCNT
— Enable the timer 1 interrupt
— Clear timer 1 interrupt pending conditions
TACON is located in set 1, bank 0, at address EBH, and is read/write addressable using register addressing
mode.
A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency
of fxx/256, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during the normal
operation by writing a "1" to TACON.3.
To enable the timer 1 interrupt (IRQ1, vector E6H), you must write TACON.7, TACON.2, and TACON.1 to "1".
To generate the exact time interval, you should set TACON.3 and TACON.0 to “10B”, which clear counter and
interrupt pending bit. When the T1INT sub-routine is serviced, the pending condition must be cleared by software
by writing a "0" to the timer 1 interrupt pending bit, TACON.0.
Timer 1 Control Register (TACON)
EBH, Set 1, Bank 0, R/W
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Timer 1 interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Timer 1 interrupt pending bit:
0 = No interrupt pending
0 = Clear pending bit (when write)
1 = Interrupt is pending (when read)
1 = No effect (when write)
Timer 1 counter run enable bit:
0 = Disable counter running
1 = Enable counter running
Timer 1 counter clear bit:
0 = No affect
1 = Clear the timer 1 counter (when write)
Timer 1 operation mode selection bit:
0 = Two 8-bit timers mode (Timer A/B)
1 = One 16-bit timer mode (Timer 1)
Timer 1 clock selection bits:
000 = fxx/256
001 = fxx/64
010 = fxx/8
011 = fxx
111 = T1CLK
(external clock rising edge)
Figure 11-1. Timer 1 Control Register (TACON)