S3C825A/P825A
CONTROL REGISTER
4-1
4
CONTROL REGISTERS
OVERVIEW
In this chapter, detailed descriptions of the S3C825A control registers are presented in an easy-to-read format.
You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates
the important features of the standard register description format.
Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed
information about control registers is presented in the context of the specific peripheral hardware descriptions in
Part II of this manual.
Data and counter registers are not described in detail in this reference chapter. More information about all of the
registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this
manual.
The locations and read/write characteristics of all mapped registers in the S3C825A register file are listed in
Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, “
RESET and Power-
Down."
Table 4-1. Set 1 Registers (INTPND/STPCON/OSCCON are in bank 0 of set 1)
Register Name
Mnemonic
Address
R/W
RESET
RESET Values (bit)
Decimal
Hex
7
6
5
4
3
2
1
0
Interrupt pending register
INTPND
208
D0H
R/W
–
0
STOP control register
STPCON
209
D1H
R/W
0
Oscillator control register
OSCCON
210
D2H
R/W
–
0
–
0
Basic timer control register
BTCON
211
D3H
R/W
0
System clock control register
CLKCON
212
D4H
R/W
0
System flags register
FLAGS
213
D5H
R/W
x
0
Register pointer 0
RP0
214
D6H
R/W
1
0
–
Register pointer 1
RP1
215
D7H
R/W
1
0
1
–
Stack pointer (high byte)
SPH
216
D8H
R/W
x
Stack pointer (low byte)
SPL
217
D9H
R/W
x
Instruction pointer (high byte)
IPH
218
DAH
R/W
x
Instruction pointer (low byte)
IPL
219
DBH
R/W
x
Interrupt request register
IRQ
220
DCH
R
0
Interrupt mask register
IMR
221
DDH
R/W
x
System mode register
SYM
222
DEH
R/W
0
–
x
0
Register page pointer
PP
223
DFH
R/W
0