16-BIT TIMER 3
S3C825A/P825A
13-2
T3CON is located in set 1, bank 0, at address F8H, and is read/write addressable using Register addressing
mode.
A reset clears T3CON to “00H”. This sets timer 3 to normal interval timer mode, selects an input clock frequency
of fxx/1024, and disables all timer 3 interrupts. You can clear the timer 3 counter at any time during normal
operation by writing a "1" to T3CON.2.
The timer 3 overflow interrupt (T3OVF) is interrupt level IRQ2 and has the vector address ECH. When a timer 3
overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware
or must be cleared by software.
To enable the timer 3 match/capture interrupt (IRQ2, vector EAH), you must write T3CON.1 to "1". To detect a
match/capture interrupt pending condition, the application program polls INTPND.3. When a "1" is detected, a
timer 3 match or capture interrupt is pending. When the interrupt request has been serviced, the pending
condition must be cleared by software by writing a "0" to the timer 3 match/capture interrupt pending bit,
INTPND.3.
Timer 3 Control Register (T3CON)
F8H, Set 1, Bank 0, R/W
.7
.6
.5
.4
.3
.2
.1
.0
MSB
LSB
Timer 3 counter clear bit:
0 = No effect
1 = Clear the timer 3 counter (when write)
Timer 3 input clock selection bits:
000 = fxx/1024
001 = fxx/256
010 = fxx/64
011 = fxx/8
100 = fxx
101 = External clock
(P3.5/T3CLK) falling edge
110 = External clock
(P3.5/T3CLK) rising edge
111 = Counter stop
Timer 3 operating mode selection bits:
00 = Interval mode (P3.6/T3OUT)
01 = Capture mode (capture on rising edge,
counter running, OVF can occur)
10 = Capture mode (capture on falling edge,
counter running, OVF can occur)
11 = PWM mode (OVF and match interrupt can occur)
Timer 3 overflow interrupt enable bit:
0 = Disable overflow interrupt
1 = Enable overflow interrupt
Timer 3 match/capture interrupt enable bit:
0 = Disable interrupt
1 = Enable interrupt
Figure 13-1. Timer 3 Control Register (T3CON)