参数资料
型号: S3P9664-SK
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO20
封装: 0.300 INCH, SOP-20
文件页数: 139/148页
文件大小: 784K
代理商: S3P9664-SK
BASIC TIMER and TIMER 0
S3C9664/P9664 (Preliminary Spec)
10-6
TIMER 0 CONTROL REGISTER (T0CON) AND INTERRUPT CONTROL REGISTER(T0INT)
You use the timer 0 control register (T0CON) and the timer 0 interrupt control register (T0INT), to
— Select the timer 0 operating mode (interval timer, capture mode, or PWM mode)
— Select the timer 0 input clock frequency
— Clear the timer 0 counter, T0CNT
— Enable the timer 0 overflow interrupt and timer 0 match/capture interrupts
— Clear timer 0 match/capture interrupt pending conditions
T0CON is located at address D2H and T0INT at address D3H, both are read/write addressable using Register
addressing mode.
A reset clears T0CON and T0INT to "00H". This sets timer 0 to normal interval timer mode, selects an input clock
frequency of f
OSC/4096, and disables the timer 0 overflow interrupt and match/capture interrupts. You can clear
the timer 0 counter at any time during the normal operation by writing a "1" to T0CON.3.
When a timer 0 overflow interrupt occurs and is serviced by the CPU, the pending condition is to be cleared by
Software. To enable the timer 0 match/capture interrupt, you must write T0INT.2 to "1". To detect an interrupt
pending condition, the application program polls T0INT.0. When a "1" is detected, a timer 0 match/capture
interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by
software by writing a "0" to the timer 0 interrupt pending bit, T0INT.0.
For a timer 0 overflow interrupt, like the way of handing timer 0 match/capture interrupt, you have to write
T0INT.3 to “1” to be enabled. timer 0 overflower pending condition can be detected on the condition of TOINT.1
being set to “1” when the application program polls T0INT.1.and the pending condition must be cleared by
software by writing T0INT.1 a “0” when the interrupt request has been serviced.
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