94
PRELIMINARY
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
A
.
HITM#
I/O
GTL+
HIT MODIFIED. HITM# indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for providing the line. Also,
driven in conjunction with HIT# to extend the snoop window.
REQ[4:0]#
I
GTL+
REQUEST. In the first cycle of a request these signals carry the request type. In the
second cycle they carry the data size and transfer length.
RP#
I
GTL+
REQUEST PARITY. RP# is even parity that covers REQ[4:0]# and ADS#. RP# is valid
on both cycles of the request.
RS[2:0]#
I/O
GTL+
RESPONSE. RS[2:0]# encode the response to a request.
RSP#
I/O
GTL+
RESPONSE PARITY. RSP# provides response parity for RS[2:0]#.
TRDY#
I/O
GTL+
TARGET READY. TRDY# is driven by the target of the data to indicate it is ready to
receive data.
Table 2. Memory Address/Control Interface Signals (DC)
Signal
Type
Description
CASA[3:0]#
CASB[3:0]#
O
CMOS
COLUMN ADDRESS STROBE (TWO COPIES). Indicates that the address on
MA[12:0] is the column address. There is one CAS# per logical row of memory. Two
copies are provided to support external loading.
CASA[7:0]#
CASB[7:0]#
MAA[12:0]
MAB[12:0]
O
CMOS
MEMORY ADDRESS (TWO COPIES). Multiplexed row and column memory
address. Two copies are provided to support external loading.
RASA[3:0]#
RASB[3:0]#
O
CMOS
ROW ADDRESS STROBE (TWO COPIES). Indicates that the address on MA[12:0]
is the row address. There is one RAS# per logical row of memory. Two copies are
provided to support external loading.
RASA[7:0]#
RASB[7:0]#
WE0#
WE1#
O
CMOS
WRITE ENABLE (TWO COPIES). Indicates that the current memory request is a
write. Two copies are provided to support external loading.
Table 3. DC/DP Interchip Signals (DC)
Signal
Type
Description
MEMCMD[7:0]#
I/O
CMOS
MEMORY SIDE COMMAND. These signals transfer command and configu-
ration information between the DC and DP.
MEMERR[1:0]#
I
CMOS
MEMORY ERROR. These signals transfer memory error information from the
DP to the DC.
Table 1. Host Bus Address/Control Interface Signals (DC) (Continued)
Signal
Type
Description