96
PRELIMINARY
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
A
1.2
DP Signals
.
Table 7. Test Signals (DC)
Signal
Type
Description
GTLHI
I/O
GTL+
These signals must be tied to VTT using a 10K resistor for proper operation in
both test and normal operating modes.
TCK
I
CMOS
JTAG Test Clock. When TMS is tied low, this signal has no effect on normal
operation.
TDI
I
CMOS
JTAG Test Data In. When TMS is tied low, this signal has no effect on normal
operation.
TDO
O
CMOS
JTAG Test Data Out. When TMS is tied low, this signal has no effect on normal
operation.
TESTHI
I/O
TEST HIGH. These signals must be tied high using a 10K
resistor for proper
operation in both test and normal operating modes.
TESTLO
I/O
TEST LOW. These signals must be tied low using a 1K
resistor for proper
operation in both test and normal operating modes.
TMS
I
CMOS
JTAG Test Mode Select. This signal must be tied low for normal operation.
TRST#
I
CMOS
JTAG Test Reset. When TMS is tied low, this signal has no effect on normal
operation.
RECVEN
I
RECEIVER ENABLE. This function is useful for component test. This signal is
negated with PWRGOOD to disable GTL+ receivers and tri-state outputs for
board test.
Table 8. Host Bus Interface Signals (DP)
Signal
Type
Description
D[63:0]#
I/O
GTL+
DATA BUS. The data bus consists of eight bytes.
DEP[7:0]#
I/O
GTL+
DATA ECC/PARITY. DEP[7:0]# provides ECC for the D[63:0]# signals. ECC is
computed over the 64 data bits. Parity is not generated or checked by the MC.
DRDY#
I/O
GTL+
DATA READY. Asserted for each cycle that data is transferred.
Table 9. Data Path Interface Signals (DP)
Signal
Type
Description
MDE[71:0]
I/O
CMOS
MEMORY DATA AND ECC. Common to all types and sizes of memory supported,
these signals include the 64 bits of data and 8 ECC check bits. ECC is computed
over 64-bit data words. Parity is computed as byte-parity over a 64-bit word.
MDRDY0#
MDRDY1#
O
CMOS
MEMORY DATA READY (TWO COPIES). Asserted when write data on the MDE
bus is valid. Two copies are provided to support external loading.