![](http://datasheet.mmic.net.cn/140000/S82451KX_datasheet_5011683/S82451KX_103.png)
PRELIMINARY
95
A
82453KX/GX, 82452KX/GX, 82451KX/GX (MC)
SYSCMD[4:0]#
O
CMOS
SYSTEM SIDE COMMAND. These signals send commands and other
information from the DC to the DP.
SYSDEN#
O
CMOS
SYSTEM SIDE DATA ENABLE. This signal permits the DC to control the
enabling of DP data information onto the host bus.
SYSERR#
I
CMOS
SYSTEM ERROR. This signal sends system error data conditions from the DP
to the DC.
Table 4. DC/MIC Interchip Signals (DC)
Signal
Type
Description
MICCMD[6:0]#
O
CMOS
MIC COMMAND. Sends read/write/configuration commands to the MIC.
MICMWC[1:0]#
O
CMOS
MIC MEMORY WRITE COMMAND (TWO COPIES). Instructs the MIC to drive
write data held in its internal buffers on the memory data bus.
Table 5. Reset and Error Signals (DC)
Signal
Type
Description
BINIT#
I/O
GTL+
BUS INITIALIZATION. BINIT# is asserted to initialize the host bus. Configuration
registers are not affected.
MIRST#
O
CMOS
MEMORY INTERFACE RESET. The DC uses this signal to reset the DP and MIC.
RESET#
I
GTL+
RESET. This is a hard reset to the DC. The DC sets its internal registers to their
default conditions and asserts the MIRST# to the DP and MICs.
SBCERR#
O
CMOS
SINGLE BIT CORRECTED ERROR. When SBC error reporting is enabled in the
MERRCMD or SERRCMD Register, this signal is asserted to indicate that a single
bit error was detected and corrected in the memory array.
Table 6. Clock, Power, and Support SIgnals (DC)
Signal
Type
Description
BCLK
I
CMOS
BUS CLOCK. This is the input clock for the DC.
GTLREFV
I
Analog
GTL REFERENCE VOLTAGE. GTLREFV sets the voltage level used by the GTL
input receivers for comparison against incoming GTL level signals.
OMCNUM
I
CMOS
MEMORY CONTROLLER NUMBER. During a power-on reset, this signal
provides the MC device number (see MCNUM Register).
PWRGD
I
CMOS
POWER GOOD. PWRGD is provided by the power supply when all voltages have
stabilized for at least 1 ms.
Table 3. DC/DP Interchip Signals (DC) (Continued)
Signal
Type
Description