参数资料
型号: SAA7706H/N210,518
厂商: NXP Semiconductors
文件页数: 21/52页
文件大小: 0K
描述: IC CAR RADIO DSP 80-QFP
标准包装: 500
类型: 汽车信号处理器
接口: I²C,I²:S,LSB,SPDIF
电压 - 输入/输出: 3.30V
电压 - 核心: 3.30V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 80-BQFP
供应商设备封装: 80-QFP(14x20)
包装: 带卷 (TR)
其它名称: 935270285518
SAA7706H/N210-T
SAA7706H/N210-T-ND
2001 Mar 05
28
Philips Semiconductors
Product specication
Car radio Digital Signal Processor (DSP)
SAA7706H
handbook, full pagewidth
10
70
50
54
62
MGT472
58
64
52
60
56
30
20
10
60
50
40
0
f (kHz)
α
(dB)
Fig.17 Detailed frequency response curve RDS channel.
The quadrature mixer converts the RDS band to the
frequency spectrum around 0 Hz and contains the
appropriate Q/I signal filters. The final decoder with
CORDIC recovers the clock and data signals. These
signals are output on pins RDS_CLOCK and RDS_DATA.
In the event of FM-stereo reception the clock of the total
chip is locked to the stereo pilot (19 kHz multiple). In the
event of FM-mono the DCS loop keeps the DCS clock
around the same 19 kHz multiple. In all other cases like
AM reception or tape, the DCS circuit has to be set in a
preset position by means of an I2C-bus bit. Under these
conditions the RDS system is always clocked by the DCS
clock in a 38 kHz (4
× 9.5 kHz) based sequence.
8.15.2
TIMING OF CLOCK AND DATA SIGNALS
The timing of the clock and data output is derived from the
incoming data signal. Under stable conditions the data will
remain valid for 400
s after the clock transition. The
timing of the data change is 100
s before a positive clock
change. This timing is suited for positive as well as
negative triggered interrupts on a microcontroller. The
RDS timing is shown in Fig.18. During poor reception it is
possible that faults in phase occur, then the duty cycle of
the clock and data signals will vary from minimum
0.5 times to a maximum of 1.5 times the standard clock
periods. Normally, faults in phase do not occur on a cyclic
basis.
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