参数资料
型号: SAB-C161O-L16M
厂商: INFINEON TECHNOLOGIES AG
元件分类: 微控制器/微处理器
英文描述: 16-BIT, 16 MHz, MICROCONTROLLER, PQFP80
封装: 0.65 MM PITCH, PLASTIC, MQFP-80
文件页数: 26/43页
文件大小: 741K
代理商: SAB-C161O-L16M
1996 Intermediate Version
Semiconductor Group
31
C161
AC Characteristics (cont’d)
Multiplexed Bus
V
CC = 5 V ± 10 %;
V
SS = 0 V
T
A = 0 to +70 C
for SAB-C161V-L16M, SAB-C161K-L16M, SAB-C161O-L16M
C
L (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF
C
L (for Port 6, CS) = 100 pF
ALE cycle time = 6 TCL + 2
t
A + tC + tF (186 ns at 16-MHz CPU clock without waitstates)
Parameter
Symbol
Max. CPU Clock
= 16 MHz
Variable CPU Clock
1/2TCL = 1 to 16 MHz
Unit
min.
max.
min.
max.
ALE high time
t
5
CC 21 +
t
A
TCL - 10 +
t
A
–ns
Address setup to ALE
t
6
CC 16 + t
A
TCL - 15 +
t
A
–ns
Address hold after ALE
t
7
CC 21 + t
A
TCL - 10 +
t
A
–ns
ALE falling edge to RD,
WR (with RW-delay)
t
8
CC 21 + t
A
TCL - 10 +
t
A
–ns
ALE falling edge to RD,
WR (no RW-delay)
t
9
CC -10 + t
A
-10 +
t
A
–ns
Address float after RD,
WR (with RW-delay)
t
10
CC –
5
–5ns
Address float after RD,
WR (no RW-delay)
t
11
CC –
36
TCL + 5
ns
RD, WR low time
(with RW-delay)
t
12
CC 53 +
t
C
2TCL - 10
+
t
C
–ns
RD, WR low time
(no RW-delay)
t
13
CC 84 +
t
C
3TCL - 10
+
t
C
–ns
RD to valid data in
(with RW-delay)
t
14
SR –
43 +
t
C
2TCL - 20
+
t
C
ns
RD to valid data in
(no RW-delay)
t
15
SR –
74 +
t
C
3TCL - 20
+
t
C
ns
ALE low to valid data in
t
16
SR –
74
+
t
A + tC
3TCL - 20
+
t
A + tC
ns
Address to valid data in
t
17
SR –
95
+ 2
t
A + tC
4TCL - 30
+ 2
t
A + tC
ns
Data hold after RD
rising edge
t
18
SR 0
0–ns
Data float after RD
t
19
SR –
48 +
t
F
2TCL - 15
+
t
F
ns
Data valid to WR
t
22
SR 48 +
t
C
2TCL - 15
+
t
C
–ns
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