参数资料
型号: SC1485ITSTRT
厂商: Semtech
文件页数: 13/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 28-TSSOP
标准包装: 1
PWM 型: 控制器
输出数: 2
占空比: 90%
电源电压: 1.8 V ~ 25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 28-TSSOP(0.173",4.40mm 宽)
包装: 标准包装
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC1485ITSDKR
POWER MANAGEMENT
NOT RECOMMENDED FOR NEW DESIGN
SC1485
=
R ESR ( MIN )
?
?
V FB _ VBAT ( MIN ) = V RIPPLE _ VBAT ( MIN ) ? ? ? V P ? P
?
? R BOT +
+ 2 ? π ? f SW _ VBAT ( MIN ) ? C TOP
? ?
?
?
We will select a value of 12.5m ? maximum for our
design, which would be achieved by using two 25m ?
output capacitors in parallel. Note that for constant-on
converters there is a minimum ESR requirement for
stability which can be calculated as follows:
3
2 ? π ? C OUT ? f SW
This criteria should be checked once the output
capacitance has been determined.
Now that we know the output ESR we can calculate the
output ripple voltage:
V RIPPLE _ VBAT ( MAX ) = R ESR ? I RIPPLE _ VBAT ( MAX ) V P ? P
and
V RIPPLE _ VBAT ( MIN ) = R ESR ? I RIPPLE _ VBAT ( MIN ) V P ? P
For our example:
V RIPPLE_VBAT(MAX) = 27mV P-P and V RIPPLE_VBAT(MIN) = 22mV P-P
Note that in order for the device to regulate in a
controlled manner, the ripple content at the feedback
pin, V FB , should be approximately 15mV P-P at minimum
V BAT , and worst case no smaller than 10mV P-P . If
V RIPPLE_VBAT(MIN) is less than 15mV P-P the above component
values should be revisited in order to improve this. Quite
often a small capacitor, C TOP , is required in parallel with
the top feedback resistor, R TOP , in order to ensure that
V FB is large enough. C TOP should not be greater than
100pF. The value of C TOP can be calculated as follows,
where R BOT is the bottom feedback resistor. Firstly
calculating the value of Z TOP required:
For our example we will use R TOP = 20.0k ? and
R BOT = 14.3k ? , therefore:
Z TOP = 6.67k ? and C TOP = 60pF
We will select a value of C TOP = 56pF. Calculating the
value of V FB based upon the selected C TOP :
? ?
? ?
? R BOT ?
1
? 1 ?
R TOp
For our example:
V FB_VBAT(MIN) = 14.8mV P-P - good
Next we need to calculate the minimum output
capacitance required to ensure that the output voltage
does not exceed the transient maximum limit, POSLIM TR ,
starting from the actual static maximum, V OUT_ST_POS , when
a load release occurs:
V OUT _ ST _ POS = V OUT + ERR DC V
For our example:
V OUT_ST_POS = 1.224V
POSLIM TR = V OUT ? TOL TR V
Where TOL TR is the transient tolerance. For our example:
POSLIM TR = 1.296V
The minimum output capacitance is calculated as
= ? ( V RIPPLE _ VBAT ( MIN ) ? 0 . 015 ) Ohms
Z TOP
?
?
I
? I OUT + RIPPLE _ VBAT ( MAX ) ?
(
POSLIM TR ? V OUT _ ST _ POS
R BOT
0 . 015
Secondly calculating the value of C TOP required to achieve
this:
follows:
C OUT ( MIN )
= L ?
? ?
2
2
2
)
F
? ?
?
?
C TOP
=
? 1 1 ?
?
? Z TOP R TOP ?
2 ? π ? f SW _ VBAT ( MIN )
F
This calculation assumes the absolute worst case
condition of a full-load to no load step transient occurring
when the inductor current is at its highest. The
capacitance required for smaller transient steps my be
calculated by substituting the desired current for the I OUT
term.
? 2005 Semtech Corp.
13
www.semtech.com
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