参数资料
| 型号： | SC1485ITSTRT |
| 厂商： | Semtech |
| 文件页数： | 21/27页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 28-TSSOP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 占空比： | 90% |
| 电源电压： | 1.8 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC1485ITSDKR |
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NOT RECOMMENDED FOR NEW DESIGN
SC1485
POWER MANAGEMENT
Key points for the power section:
1) there should be a very small input loop, well decoupled.
2) the phase node should be a large copper pour, but compact since this is the noisiest node.
3) input power ground and output power ground should not connect directly, but through the ground planes instead.
4) The two outputs should not share their input capacitors, and these should have separate PWR_SRC and PGND
(component-side) copper pours.
5) The two output inductors should not be placed adjacent to each other to avoid crosstalk.
6) Notice in Figure 13 placement of 0 ? resistor at the bottom of the output capacitor to connect to VSSA1/2 for
each output.
Connecting the control and power sections should be accomplished as follows (see Figure 14 below):
1) Route VSSA1/2 and their related feedback traces as differential pairs routed in a “quiet” layer away from noise
sources.
2) Route DL, DH and LX (low side FET gate drive, high side FET gate drive and phase node) to chip using wide traces
with multiple vias if using more than one layer. These connections to be as short as possible for loop minimization,
with a length to width ratio less than 20:1 to minimize impedance. DL is the most critical gate drive, with power
ground as its return path. LX is the noisiest node in the circuit, switching between PWR_SRC and ground at high
frequencies, thus should be kept as short as practical. DH has LX as its return path.
3) BST is also a noisy node and should be kept as short as possible.
4) Connect PGND pins on the chip directly to the VDDP decoupling capacitor and then drop vias directly to the
ground plane.
5) Locate the current limit sense resistors between the LX and ILIM pins at the device.
22
23
24
25
U1
EN/PSV1
TON1
VOUT1
VCCA1
SC1485
BST1
DH1
LX1
ILIM1
7
6
5
4
R5
Q2
L1
0402
26
27
28
8
9
FB1
PGD1
VSSA1
EN/PSV2
TON2
VDDP1
DL1
PGND1
BST2
DH2
3
2
1
21
20
Q1
Q3
IRF7811AV
10
VOUT2
LX2
19
L2
2u2
R10 7k87
11
VCCA2
ILIM2
18
0402
12
13
14
FB2
PGD2
VSSA2
VDDP2
DL2
PGND2
17
16
15
Q4
FDS6676S
Figure 14: Connecting Control and Power Sections
Phase nodes (black) to be copper islands (preferred) or wide copper traces. Gate drive traces (red) and phase node
traces (blue) to be wide copper traces (L:W < 20:1) and as short as possible, with DL the most critical.
? 2005 Semtech Corp.
21
www.semtech.com
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