参数资料
| 型号： | SC1485ITSTRT |
| 厂商： | Semtech |
| 文件页数： | 16/27页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 28-TSSOP |
| 标准包装： | 1 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 占空比： | 90% |
| 电源电压： | 1.8 V ~ 25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 包装： | 标准包装 |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC1485ITSDKR |
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NOT RECOMMENDED FOR NEW DESIGN
SC1485
POWER MANAGEMENT
Layout Guidelines
One (or more) ground planes is/are recommended to minimize the effect of switching noise and copper losses, and
maximize heat dissipation. The IC ground references, VSSA1 and VSSA2, should be kept separate from power
ground. All components that are referenced to them should connect to them locally at the chip. VSSA1 and VSSA2
should connect to power ground at their respective output capacitors only .
Feedback traces must be kept far away from noise sources such as switching nodes, inductors and gate drives.
Route feedback traces with their respective VSSAs as a differential pair from the output capacitor back to the chip.
Run them in a “quiet layer” if possible.
Chip decoupling capacitors (VDDP, VCCA) should be located next to the pins and connected directly to them on the
same side.
Power sections should connect directly to the ground plane(s) using multiple vias as required for current handling
(including the chip power ground connections). Power components should be placed to minimize loops and reduce
losses. Make all the connections on one side of the PCB using wide copper filled areas if possible. Do not use
“minimum” land patterns for power components. Minimize trace lengths between the gate drivers and the gates of
the MOSFETs to reduce parasitic impedances (and MOSFET switching losses), the low-side MOSFET is most critical.
Maintain a length to width ratio of <20:1 for gate drive signals. Use multiple vias as required by current handling
requirement (and to reduce parasitics) if routed on more than one layer
Current sense connections must always be made using Kelvin connections to ensure an accurate signal.
We will examine the SC1485 OUT2 reference design used in the Design Procedure section while explaining the
layout guidelines in more detail, using the same generic components for OUT1.
5VSUS
VBAT
VBAT
5VSUS
R1
0402
R2
10R
0402
22
23
U1
EN/PSV1
TON1
SC1485
BST1
DH1
7
6
D1
SOD323
C5 0.1uF
0603
Q2
C6
2n2/50V
0402
C1
0u1/25V
0603
C2
10u/25V
1210
PGOOD
C4
1nF
0402
C7
0402
VOUT1
R4
0402
R3
0402
C9
1uF
0603
24
25
26
27
28
VOUT1
VCCA1
FB1
PGD1
VSSA1
LX1
ILIM1
VDDP1
DL1
PGND1
5
4
3
2
1
R5
0402
C10
1uF
0603
Q1
L1
R6 0R (1)
0402
VSSA1
+
C8
7343
+
C3
7343
VOUT1
VBAT
5VSUS
VSSA1
5VSUS
VBAT
R7
1M
0402
R8
10R
0402
8
9
EN/PSV2
TON2
BST2
DH2
21
20
D2
SOD323
C11 0.1uF
Q3
IRF7811AV
0603
C12
2n2/50V
0402
C13
0u1/25V
0603
C14
10u/25V
1210
PGOOD
C18
1nF
0402
C15
56p
0402
VOUT2
R9
20k0
0402
R13
20k0
0402
C19
1uF
0603
10
11
12
13
14
VOUT2
VCCA2
FB2
PGD2
VSSA2
LX2
ILIM2
VDDP2
DL2
PGND2
N OTES
19
18
17
16
15
R10 7k87
0402
C20
1uF
0603
Q4
FDS6676S
L2 2u2
R12 0R (1)
0402
VSSA2
+
C16
220u/25m
7343
+
VOUT2
C17
220u/25m
7343
VSSA2
(1) R 6 and R 12 aid in k eeping VSSA1 and VSSA2 s eparate f rom PGN D ex c ept where des ired in lay out.
Figure 8: Reference Design and Layout Example
? 2005 Semtech Corp.
16
www.semtech.com
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