参数资料
型号: SC16IS850LIPW
厂商: NXP Semiconductors N.V.
元件分类: 连接器件
英文描述: Single UART with I2C-bus-SPI interface, 128 bytes of transmit and receive FIFOs, IrDA SIR built-in support
封装: SC16IS850LIBS<SOT616-3 (HVQFN24)|<<http://www.nxp.com/packages/SOT616-3.html<1<Always Pb-free,;SC16IS850LIBS<SOT616-3 (HVQFN24)|<<http://www.nxp.com/packages/SOT616-3.htm
文件页数: 5/60页
文件大小: 755K
代理商: SC16IS850LIPW
SC16IS850L
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 22 July 2011
5 of 60
NXP Semiconductors
SC16IS850L
Single UART with I
2
C-bus/SPI interface
V
SS
I2C/SPI
9
[1]
2
6
23
-
I
Power ground.
I
2
C-bus or SPI interface select.
I
2
C-bus interface is selected if this pin is at
logic HIGH. SPI interface is selected if this pin is
at logic LOW.
This pin has an internal pull-up resistor, and can
be left unconnected if I
2
C-bus mode is selected.
SPI chip select or I
2
C-bus device address select
A0.
If SPI configuration is selected by I2C/SPI pin,
this pin is the SPI chip select pin (Schmitt-trigger,
active LOW). If I
2
C-bus configuration is selected
by I2C/SPI pin, this pin along with A1 pin allows
user to change the device’s base address.
For I
2
C-bus slave address configuration, please
refer to
Table 33
.
SPI data input pin or I
2
C-bus device address
select A1.
If SPI configuration is selected by I2C/SPI pin,
this is the SPI data input pin. If I
2
C-bus
configuration is selected by I2C/SPI pin, this pin
along with A0 pin allows user to change the
device’s base address.
For I
2
C-bus slave address configuration, please
refer to
Table 33
SPI data output pin. If SPI configuration is
selected by I2C/SPI pin, this is a 3-stateable
output pin. If I
2
C-bus configuration is selected by
I2C/SPI pin, this pin function is undefined and
must be left as n.c. (not connected).
I
2
C-bus or SPI input clock.
I
2
C-bus data input/output, open-drain if I
2
C-bus
configuration is selected by I2C/SPI pin. If SPI
configuration is selected then this pin is an
undefined pin and must be connected to V
SS
.
Interrupt (open-drain, active LOW).
Interrupt is enabled when interrupt sources are
enabled in the Interrupt Enable Register (IER).
Interrupt conditions include: change of state of
the input pins, receiver errors, available receiver
buffer data, available transmit buffer space, or
when a modem status flag is detected.
An external 10 k
resistor must be connected
between this pin and V
DD
.
CS/A0
14
11
I
SI/A1
13
10
I
SO
1
22
O
SCL/SCLK
SDA
3
24
24
21
I
I/O
IRQ
15
12
O
Table 2.
Symbol
Pin description
…continued
Pin
HVQFN24
Type
Description
TSSOP24
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