参数资料
型号: SC195ULTRT
厂商: Semtech
文件页数: 13/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.5A 8MLPQ
特色产品: SC195 Buck Regulator
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 3.3 V
输入电压: 2.9 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 3.5MHz
电流 - 输出: 500mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-MLPQ
包装: 标准包装
供应商设备封装: 8-MLPQ-UT(1.5x1.5)
产品目录页面: 1357 (CN2011-ZH PDF)
其它名称: SC195ULDKR
SC195
Applications Information (continued)
V IN
Enable
C IN
SC195
IN
CTL3
CTL2
CTL1
LX
OUT
GND
L X
C FF
R FB1
R FB2
C OUT
V OUT
increases as V IN decreases to maintain output voltage
regulation. As the input voltage approaches the pro-
grammed output voltage, the duty cycle approaches
100% (PMOS always on) and the device enters a pass-
through mode until the input voltage increases or the
load decreases enough to allow PWM switching to
resume.
V OUT
0 . 5
C FF
8 10
CTL0
Figure 1 — Application Circuit with External Resistors
To simplify the design, it is recommended to program the
output setting to 1.0V, use resistor values smaller than
10kΩ, and include a feed-forward capacitance calculated
with the equation above. If the output voltage is set to
1.0V, the previous equation reduces to
2
6
R FB 1 V OUT 1
Example:
An output voltage of 1.3V is desired, but this is not a pro-
grammable option. What external component values for
Figure 1 are needed?
Solution: To keep the circuit simple, set R FB2 to 10kΩ so
current into the OUT pin can be neglected and set the
CTL3-0 pins to 0010 (1.0V setting). The necessary compo-
nent values for this situation are
Power Save Mode Operation
When the load current decreases below the PSAVE
threshold, PWM switching stops and the device auto-
matically enters PSAVE mode. This threshold varies
depending on the input voltage and output voltage
setting, optimizing efficiency for all possible load currents
in PWM or PSAVE mode. While in PSAVE mode, output
voltage regulation is controlled by a series of switching
bursts. During a burst, the inductor current is limited to a
peak value which controls the on-time of the PMOS
switch. After reaching this peak, the PMOS switch is dis-
abled and the inductor current decreases to near 0mA.
Switching bursts continue until the output voltage climbs
to V OUT +2.5% or until the PSAVE current limit is reached.
Switching is then stopped to eliminate switching losses,
enhancing overall efficiency. Switching resumes when
the output voltage reaches the lower threshold of V OUT
and continues until the upper threshold again is reached.
Note that the output voltage is regulated hysteretically
while in PSAVE mode between V OUT and V OUT + 2.5%. The
period and duty cycle while in PSAVE mode are solely
determined by V IN and V OUT until PWM mode resumes. This
can result in the switching frequency being much lower
R FB 1
R FB 2
V OUT V SET
V SET
V OUT
0 . 5
C FF
8 10
6
PWM Operation
R FB 1 V OUT 1
3 k
2
5 . 69 nF
than the PWM mode frequency.
If the output load current increases enough to cause V OUT
to decrease below the PSAVE exit threshold (V OUT -2%),
the device automatically exits PSAVE and operates in
continuous PWM mode. Note that the PSAVE high and
low threshold levels are both set at or above V OUT to mini-
mize undershoot when the SC195 exits PSAVE. Figure 2
illustrates the transitions from PWM mode to PSAVE
Normal PWM operation occurs when the output load
mode and back to PWM mode.
current exceeds the PSAVE threshold. In this mode, the
PMOS high side switch is activated with the duty cycle
required to produce the output voltage programmed by
the CTL pins. An internal synchronous NMOS rectifier
eliminates the need for an external Schottky diode on the
LX pin. The duty cycle (percentage of time PMOS is active)
13
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