参数资料
型号: SC195ULTRT
厂商: Semtech
文件页数: 17/20页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 0.5A 8MLPQ
特色产品: SC195 Buck Regulator
标准包装: 1
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 0.8 V ~ 3.3 V
输入电压: 2.9 V ~ 5.5 V
PWM 型: 电压模式
频率 - 开关: 3.5MHz
电流 - 输出: 500mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-MLPQ
包装: 标准包装
供应商设备封装: 8-MLPQ-UT(1.5x1.5)
产品目录页面: 1357 (CN2011-ZH PDF)
其它名称: SC195ULDKR
SC195
Applications Information (continued)
The input voltage ripple is at maximum level when the
input voltage is twice the output voltage (50% duty cycle
scenario).
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the PMOS switch.
Low ESR/ESL X5R ceramic capacitors are recommended
for this function. To minimize stray inductance, the capaci-
tor should be placed as closely as possible to the IN and
GND pins of the SC195. Table 4 lists the recommended
input capacitor options from different manufacturers.
Table 4 — Recommended Input Capacitors
2. Keep the LX pin traces as short as possible to minimize
pickup of high frequency switching edges to other
parts of the circuit. C OUT and L X should be connected
as close as possible between the LX and GND pins,
with a direct return to the GND.
3. Use a ground plane referenced to the GND pin. Use
several vias to connect to the component side ground
to further reduce noise and interference on sensitive
circuit nodes.
4. Route the output voltage feedback/sense path away
from the inductor and LX node to minimize noise and
magnetic interference.
5. Minimize the resistance from the OUT and GND pins
Manufacturer
Part Nunber
Murata 
GRM188R60J475K
Murata 
GRM188R60J106K
Taiyo Yuden
JMK107BJ475KA
Value
(μF)
4.7±10%
10±10%
4.7±10%
Type
X5R
X5R
X5R
Rated
Voltage
(VDC)
6.3
6.3
6.3
Dimensions
LxWxH (mm)
Case Size
1.6x0.8x0.8
0603
1.6x0.8x0.8
0603
1.6x0.8x0.8
0603
to the load. This will reduce errors in DC regulation
due to voltage drops in the traces.
4.8mm
C IN
TDK
C1608X5R0J475KT
4.7±10%
X5R
6.3
1.6x0.8x0.8
0603
3mm
CTL3
L X
PCB Layout Considerations
The layout diagram in Figure 3 shows a recommended
PCB top-layer for the SC195 and supporting components.
CTL2
CTL1
CTL0
SC195
C OUT
Specified layout rules must be followed since the layout is
critical for achieving the performance specified in the
Electrical Characteristics table. Poor layout can degrade
the performance of the DC-DC converter and can contrib-
ute to EMI problems, ground bounce, and resistive voltage
Figure 3 — Recommended PCB Layout
losses. Poor regulation and instability can result.
The following guidelines are recommended for designing
a PCB layout:
1. C IN should be placed as close to the IN and GND pins
as possible. This capacitor provides a low impedance
loop for the pulsed currents present at the buck
converter’s input. Use short wide traces to minimize
trace impedance. This will also minimize EMI and
input voltage ripple by localizing the high frequency
current pulses.
17
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