参数资料
| 型号： | SC419ULTRT |
| 厂商： | Semtech |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 20-MLPQ |
| 标准包装： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 3 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-MLPQ |
| 包装： | 标准包装 |
| 其它名称： | SC419ULTRTDKR |
SC419
Applications Information (continued)
The current limit schematic with the R ILIM resistor is shown
in Figure 9.
V IN
Power Good Output
The PGOOD (Power Good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the
FB pin is 10% below the nominal voltage, PGOOD is pulled
BST
DH
LX
ILIM
DL
PGND
C BST
R ILIM
Q1
Q2
+
CIN
L
D2
C OUT
+
V OUT
low. It is held low until the FB voltage returns above -8%
of nominal. PGOOD is held low during start-up and will
not be allowed to transition high until soft-start is com-
pleted (when V FB reaches 500mV). The delay time starting
from EN going high is typically 2ms.
PGOOD will transition low if the FB voltage exceeds +20%
of nominal, which is also the over-voltage threshold
(600mV). PGOOD also pulls low if the EN pin is low when
VDDA is present.
Figure 9 — Valley Current Limit
Setting the valley current limit to 10A results in a peak
inductor current of 10A plus peak ripple current. In this
situation the average current through the inductor is 10A
plus one-half the peak-to-peak ripple current.
The R ILIM value is calculated by the next equation.
Output Over-Voltage Protection
OVP (Over-voltage protection) becomes active as soon as
the device is enabled. The OVP threshold is set at 500mV
+ 20% (600mV). When V FB exceeds the OVP threshold, DL
latches high and the low-side MOSFET is turned on. DL
remains high and the controller remains off until the EN
input is toggled or VDDA is cycled. There is a 5μs delay
R ILIM
R DSON I LIM
10 A
built into the OVP detector to prevent false transitions.
PGOOD is also low after an OVP event.
Soft-Start of PWM Regulator
Soft-start is achieved in the PWM regulator by using an
internal voltage ramp as the reference for the FB compara-
tor. The voltage ramp is generated using an internal
charge pump which drives the reference from zero to
500mV in 1.2mV increments, using an internal 500kHz
oscillator. When the ramp voltage reaches 500mV, the
ramp is ignored and the FB comparator switches over to a
fixed 500mV threshold. During soft-start the output
voltage tracks the internal ramp, which limits the start-up
inrush current and provides a controlled soft-start profile.
Typical soft-start ramp time is 850μs.
During soft-start the regulator turns off the low-side
MOSFET on any cycle if the inductor current falls to zero,
Output Under-Voltage Protection
When V FB falls 25% below its nominal voltage (falls to
375mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tri-
state the MOSFETs. The controller stays off until EN is
toggled or VDDA is cycled.
VDDA UVLO and POR
The VDDA Under-Voltage Lock-Out (UVLO) circuitry inhib-
its switching and tri-states the DH/DL drivers until VDDA
rises above 3.9V. When VDDA exceeds 3.9V, an internal
POR (Power-On Rese) resets the fault latch and the soft-
start counter and then the SC419 begins the soft-start
cycle. The device will shut off if VDDA falls below 3.6V.
VDDP does not have ULVO protection.
regardless of the PSAVE mode setting. This prevents nega-
tive inductor current, allowing the device to start into a
pre-biased output.
15
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