参数资料
| 型号： | SC419ULTRT |
| 厂商： | Semtech |
| 文件页数： | 19/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 20-MLPQ |
| 标准包装： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 3 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-MLPQ |
| 包装： | 标准包装 |
| 其它名称： | SC419ULTRTDKR |
SC419
Applications Information (continued)
E SR MIN
charging during the switching cycle. For most applica-
tions the ripple voltage is dominated by the ESR of the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching fre-
quency. The formula for minimum ESR is shown by the
following equation.
3
2 C OUT f sw
When applications use ceramic output capacitors, the ESR
is normally too small to meet the minimum ESR criteria. In
these applications it is necessary to add a small virtual ESR
network composed of two capacitors and one resistor, as
shown in Figure 11. This network creates a ramp voltage
across C L , analogous to the ramp voltage generated across
the ESR of a standard capacitor. This ramp is then capaci-
tively coupled into the FB pin via capacitor C C .
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case
dropout duty-factor calculations.
System DC Accuracy
Three factors affect V OUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line
and load, and the external resistor tolerance. The error
comparator offset is trimmed so that under static condi-
tions it trips when the feedback pin is 500mV, 1%.
The on-time pulse from the SC419 in the design example
is calculated to give a pseudo-fixed frequency of 250kHz.
Some frequency variation with line and load is expected.
This variation changes the output ripple voltage. Because
adaptive on-time converters regulate to the valley of the
output ripple, ? of the output ripple appears as a DC regu-
lation error. For example, if the output ripple is 50mV with
V IN = 6 volts, then the measured DC output will be 25mV
above the comparator trip point. If the ripple increases to
High-
side
R L
L
C L
80mV with V IN = 25V, then the measured DC output will be
40mV above the comparator trip. The best way to mini-
mize this effect is to minimize the output ripple.
Low-
side
C C
FB
pin
R1
R2
C OUT
To compensate for valley regulation, it may be desirable to
use passive droop. Take the feedback directly from the
output side of the inductor and place a small amount of
trace resistance between the inductor and output capaci-
tor. This trace resistance should be optimized so that at
full load the output droops to near the lower regulation
Figure 11 — Virtual ESR Ramp Current
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is limited by the fixed 250ns (typical)
minimum off-time of the one-shot. When working with
low input voltages, the duty-factor limit must be calcu-
lated using worst-case values for on and off times.
The duty-factor limitation is shown by the following
equation.
limit. Passive droop minimizes the required output capaci-
tance because the voltage excursions due to load steps
are reduced as seen at the load.
The use of 1% feedback resistors contributes up to 1%
error. If tighter DC accuracy is required, 0.1% resistors
should be used.
The output inductor value may change with current. This
will change the output ripple and therefore will have a
minor effect on the DC output voltage. The output ESR
also affects the output ripple and thus has a minor effect
DUTY
T ON ( MIN )
T ON ( MIN ) T OFF ( MAX )
on the DC output voltage.
19
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