参数资料
| 型号： | SC419ULTRT |
| 厂商： | Semtech |
| 文件页数： | 18/24页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 20-MLPQ |
| 标准包装： | 1 |
| 系列： | EcoSpeed®, SmartDrive™ |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1MHz |
| 电源电压： | 3 V ~ 28 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 20-MLPQ |
| 包装： | 标准包装 |
| 其它名称： | SC419ULTRTDKR |
SC419
Applications Information (continued)
I LPK I MAX
V OUT
dl LOAD
I MAX =maximumloadrelease=10A
L dt
C OUT I LPK
2 V PK V OUT
Example
increase the ESR of the output capacitors. It is also impera-
tive to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small capacitor across the upper feedback resistor, as
shown in Figure 10. This capacitor should be left unpopu-
lated unless it can be confirmed that double-pulsing
dl LOAD
dt
2 . 5 A
s
exists. Adding the C TOP capacitor will couple more ripple
into FB to help eliminate the problem. An optional con-
nection on the PCB should be available for this capacitor.
This would cause the output current to move from 10A to
zero in 4μs. The output capacitance required in this case
is shown by the following equation.
C TOP
0 . 88 H
C OUT
12 . 2
12 . 2 10
1 . 05 2 . 5
2 1 . 15 1 . 05
1 s
V OUT
R1
R2
To FB pin
C OUT = 379 μF
Note that C OUT is much smaller in this example, 379μF
compared to 595μF based on a worst-case load release. To
meet the two design criteria of minimum 379μF and
maximum 9m? ESR, select two capacitors rated at 220μF
and 15m? ESR.
It is recommended that an additional small capacitor be
placed in parallel with C OUT in order to filter high frequency
switching noise.
Stability Considerations
Unstable operation is possible with adaptive on-time con-
trollers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250ns minimum off-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect opera-
tion. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 10mVp-p, which may dictate the need to
Figure 10 — Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking sta-
bility is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
One simple way to solve this problem is to add trace resis-
tance in the high current output path. A side effect of
adding trace resistance is decreased load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insuffi-
cient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and dis-
18
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