参数资料
型号: SC4525ASETRT
厂商: Semtech
文件页数: 10/19页
文件大小: 0K
描述: IC REG BUCK 3A 8SOIC
标准包装: 1
类型: 降压(降压)
输出数: 1
输入电压: 8 V ~ 28 V
PWM 型: 电流模式
频率 - 开关: 300kHz ~ 1.3MHz
电流 - 输出: 3A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm Width)裸露焊盘
包装: 标准包装
供应商设备封装: 8-SOIC-EP
产品目录页面: 1358 (CN2011-ZH PDF)
其它名称: SC4525ASEDKR
SC4525A
R 4 = R 6 ?
? V O ?
down switching . 0 V regulator in continuous-conduction
? 1 ?
V O + V D
V IN + V D ? V CESAT
diode. D I = ( V O + V D ) ? ( 1 ? D )
F SW ? L 1
L 1 =
ApplicationsInformation(Cont.)
As the load draws more current from the regulator, the
current-limit comparator ILIM (Figure 2) will eventually
limit the switch current on a cycle-by-cycle basis. The
over-current signal OC goes high, setting the latch B 3 . The
soft-start capacitor is discharged with (I D - I C ) (Figure 3). If
the inductor current falls below the current limit and the
PWM comparator instead turns off the switch, then latch
B 3 will be reset and I C will recharge the soft-start capacitor.
If over-current condition persists or OC becomes asserted
more often than PWM over a period of time, then the
soft-start capacitor will be discharged below  .9V. At this
juncture, comparator B 4 sets the overload latch B 2 . The
soft-start capacitor will be continuously discharged with
? 1 ?
mode (CCM) is given by
D = (2)
where V IN is the input voltage, V CESAT is the switch saturation
voltage, and V D is voltage drop across the rectifying
L
In peak current-mode control, the PWM modulating
( O + V D ) ( 1 ? D )
20 % I O F SW
ramp is the V sensed ? current ramp of the power switch.
This current ramp ? is ? absent unless the switch is turned
on. The intersection of this ramp with the output of the
A C =
A C =
R 7 =
C 5 =
C 8 =
(I D - I C ). The COMP pin is immediately pulled to ground. The
switching regulator is shut off until the soft-start capacitor
is discharged below  .0V. At this moment, the overload
voltage feedback error amplifier determines the switch
RMS _ CIN = I O D ? ( 1 ? D )
pulse I width. The ? propagation delay time required to
immediately turn off the switch after it is turned on is the
V o
V c
=
Fig. 4
Closed-loop = D measurement shows ? ? that the SC4525A
I L ? ? ? ESR +
D V O
latch is reset. The soft-start capacitor is recharged and
the converter again undergoes soft-start. The regulator
will go through soft-start, overload shutdown and restart
until it is no longer overloaded.
If the FB voltage falls below 0.8V because of output
minimum controllable switch on time (T ON(MIN) ).
? 1
? ? SW ? C ? ? 8
minimum on time is about F  30ns O at room temperature
(Figure 4). If the required switch on time is shorter than
the minimum on time, the regulator will either skip cycles
G PWM
R 7 =
or it will jitter.
I O
4 ? D V IN ? F SW
overload, then the switching frequency will be reduced.
Frequency foldback helps to limit the inductor current
when the output is hard shorted to ground.
SS270 REV 6-7
C IN >
Minimum On Time vs Temperature
C 5 =
During normal operation, the soft-start capacitor is
charged to 2.4V.
Setting the Output Voltage
200
190
180
170
160
V O =1.5V
1MHz
C 8 =
150
R 4 = R 6 ? ?
? 1 ? ?
V O
? 1 . 0 V
?
Setting D the Switching Frequency
V O + V D
?
V ?
1
1
A C = ? 20 120 log ? ? FB ?
0 1 1
A C = ? 20 ? log ? ?
?
? 28 ? 6 . 1 ? 10
2 π ? 80 ? 10 ? 22 ? 10
= with . 3 Ambient Temperature
R 7 =
22 k
? = 15
The regulator output voltage, V O , is set with an external
resistive divider (Figure  ) with its center tap tied to the FB
pin. For a given R 6 value, R 4 can be found by
( )
=
V IN + V D ? V CESAT
The switching frequency of the SC4525A is set with an
external resistor from the ROSC pin to ground.
140
130
? ?
110 ? G CA R S 2 π F C C O V O ?
100
-50 -25 25 50 75 100 125
? 3
Temperature ( o C) 3
15 . 9
Figure 4. Variation of Minimum On Time
10 20
0 . 28 ? 10 ? 3
? 6
?
1 . 0 ?
3 . 3 ?
Minimum L I = On Time Consideration
( V O + V D ) ? ( 1 ? D )
( V O + V D ) ? ( 1 ? D )
20 % ? I O ? F SW
C 5 =
= 0 . 45 nF
switch on time should be 10 least 20% to 30% higher than
2 ?
C 8 =
= 12 pF
D
F SW ? L 1
The operating duty cycle of a non-synchronous step-
L 1 =
1
To allow for transient headroom, the minimum operating
at
the worst-case minimum on time.
1
2 π ? 600 ? 10 3 ? 22 . 1 ? 10 3
 0
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