参数资料
| 型号： | SC4525ASETRT |
| 厂商： | Semtech |
| 文件页数： | 13/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK 3A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出数： | 1 |
| 输入电压： | 8 V ~ 28 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 300kHz ~ 1.3MHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC-EP |
| 产品目录页面： | 1358 (CN2011-ZH PDF) |
| 其它名称： | SC4525ASEDKR |
SC4525A
Applications Information (Cont.)
CONTROLLER AND SCHOTTKY DIODE
REF
+
CA
Rs
Io
Including the voltage divider (R 4 and R 6 ), the control to
feedback transfer function is found and plotted in Figure
8 as the converter gain.
FB
-
EA
Vc
Vramp
PWM
MODULATOR
SW
L1
Vo
Since the converter gain has only one dominant pole at
C5
R7
COMP
C8
Co
Resr
R4
R6
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at F Z , and a high frequency pole
at F P . The integrator is used to boost the gain at low
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
The block = = diagram log ? ? ? Figure 7 ? ? shows the ? ? control loops of a
? ? 20 ? ? log G R
A A C C
? 1 1 V FB ?
V V O O ? ? ?
? G CA R S S 2 2 π π F F C C C C O O
? the SC4525A. The inner loop (current
buck converter with
Figure7.Blockdiagramofcontrolloops
20 in ?
CA
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
1 1
1 1
1 1 . . 0 0 60 ? 15 dB
loop) consists of a current sensing resistor (R s =4. m W )
V FB ? and a current 20 ? ? log ? ? ? (CA) with gain ? ? (G CA =28). The outer ? ? 6 6
? ? 3 . 3 ? ? ? = = 15 . . 9 9 dB
?
A A C C = = ? ? 20 log
80 10 3 22
? ? loop (voltage loop) consists . . 1 1 of ? ? 10 error π π amplifier (EA), ? ? 10
? ? 28 ? ? 6 6
2 2 ? ? 80 ? ? 10 3 ? ? 22 a 10
3 . 3 ? ?
28
10
?
an
O V O ?
MP
CO
EN
1
10 1 . 0 ? 22 k
10
SA
15 . 9
TO
1 Since 3 the 1 = = current FB ? loop 3 3 ? is = = internally closed, the remaining
?
RG
20
R R 22 ? 10 ? 6 V 3 ? ? . 3 ? ? ? 15 . . 9 3 3 dB
22 k
? log π ? ? ? 80 task ? for the 0 0 loop ? ? 10
? 10 ? 7
? 7 AIN
2
?
. . 28 10
28 compensation is to design the voltage
?
Fc
OP
R S 2 π F C C O
? G CA compensator (C V , R ? , and C ).
CO
NV GA
ER
O
1 1 8
TER
C 5 = = 0 . 45 nF
45 nF
5 7 GA
C 5
10 3
2 2 π π ? ? 16 ? ? 10 3 1 ? ? 22 . . 1 1 ? ? 10 3
16 10
22
-30
? log ? ?
For a converter with switching frequency = 15 SW . , 9 dB
1 1 . 0 ?
F output
?
?
1 3 ? 22 ? 10 ? 6 3 . 3 ??
? 6 . 1 ? 10 =
C 8 = π ? 80 ? 10 1 3
? 28 inductance L 2 , output capacitance C = and pF
loading R, the
12 pF
10 3
2 2 π π ? ? 600 ? ? 10 3 ? ? 22 . . 1 1 ? ? 10 3
C 8 O = 12
600 10 22
control (V C ) to output (V O ) transfer function in Figure 7 is
= 0 . 45 nF
= 22 . 3 k V
V o = G PWM ( 1 + s R ESR C O )
? 10 12 3 pF
Figure 8. Bode plots for voltage loop design
(8)
=
= ( 1 + s / ω PWM () 1 + s / ω ESR Q + O s 2 2 / ω 2 2 )
V V c c
( 1 + s / ω p p ) ( 1 + s / ω n n Q + s / ω n n )
1
16 ? 10 3 ? This . 1 transfer function has a finite DC gain
= 0 . 45 nF
R R
1 1
1 1
1
G PWM 3 ≈ = G 12 pF , ω p ≈ R C ,
ω Z Z = = R
, ,
G CA ? R S R ESR C O
600 / ω ? 10 ) 3 ? 22 . 1 ? 10
R C O O
CA
ESR
( ) Plot the converter gain, i.e. control to feedback transfer
amplifier
? ? 3 3
PWM modulator, and a LC filter. 30 Fz1 Fp1
15 . 9
20
0 Fp
LO
IN
IN
3
Fz Fsw/2
? 3
-60
1K 10K 100K 1M 10M
15 . 9 given by: FREQUENCY (Hz)
0 20
?
3
22 ? 10 3 Therefore, the procedure of the voltage loop design for
the SC4525A can be summarized as:
G PWM ω ω
2 2
n
an ESR zero F Z at CA A C
1 G PWM ( 1 + s R ESR 7 7 C = = O ) 10 1
R
R / C ω O p ) ( 1 + s / ω n Q + s R 2 g ESR ω C n 2 O )
C C 5 5 = = π F R
a dominant 2 low-frequency pole F P at
2 π F Z Z 1 1 R 7 7
R 1 1
C 8 p = = R C O 1
2 2 π π F F P P 1 1 R R 7 7
V O
R 4 = R 6 ? ? 1 ?
A C = ? 20 ? log ? ?
? FB ? ?
? 1 1 V ?
A C = ? 20 ? log ? ?
1 1 3
?
? 28 ? 6 . 1 ? 10
2 π ? 80 ? 10 ? 22 ? 10
A ? R S C 8 R ESR C O
10 20 20
R
, ω Z = g m ,
/ m
1 1
,
, ω ≈ 1 ω Z = ,
and double poles at half the switching frequency.
? 1 . 0 V ?
function.
(2) Select the open loop crossover frequency, F C , between
0% and 20% of the switching frequency. At F C , find the
required compensator gain, A C . In typical applications with
ceramic output capacitors, the ESR zero is neglected and
the required compensator gain at F C can be estimated by
? (9)
? G CA R S 2 π F C C O V O ?
? 3 3
? 6
?
1 . 0
3 .
相关PDF资料 |
PDF描述 |
|---|---|
| SC4525CSETRT | IC REG BUCK ADJ 3A 8SOIC |
| SC4525DSETRT | IC REG BUCK ADJ 3A 8SOIC |
| SC458IMLTRT | IC REG CTRLR PWM 44-MLP |
| SC4620MLTRT | IC REG BUCK ADJ 2.5A 20MLPQ |
| SC4624AMLTRT | IC REG BUCK ADJ 4A 20MLPQ |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SC4525C | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:28V 3A Step-Down Switching Regulator Thermal Shutdown |
| SC4525CSETRT | 功能描述:IC REG BUCK ADJ 3A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 标准包装:250 系列:- 类型:降压（降压） 输出类型:固定 输出数:1 输出电压:1.2V 输入电压:2.05 V ~ 6 V PWM 型:电压模式 频率 - 开关:2MHz 电流 - 输出:500mA 同步整流器:是 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:6-UFDFN 包装:带卷 (TR) 供应商设备封装:6-SON（1.45x1） 产品目录页面:1032 (CN2011-ZH PDF) 其它名称:296-25628-2 |
| SC4525D | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:18V, 3A, 350kHz Step-Down Switching Regulator |
| SC4525DEVB | 制造商:SEMTECH 制造商全称:Semtech Corporation 功能描述:18V, 3A, 350kHz Step-Down Switching Regulator |
| SC4525DSETRT | 功能描述:IC REG BUCK ADJ 3A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 开关稳压器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:升压（升压） 输出类型:两者兼有 输出数:1 输出电压:5V，2 V ~ 16.5 V 输入电压:2 V ~ 16.5 V PWM 型:- 频率 - 开关:45kHz 电流 - 输出:50mA 同步整流器:无 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 包装:管件 供应商设备封装:8-PDIP |
发布紧急采购，3分钟左右您将得到回复。