参数资料
| 型号： | SC4525DSETRT |
| 厂商： | Semtech |
| 文件页数： | 14/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1 V ~ 16.74 V |
| 输入电压： | 3 V ~ 18 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 65kHz ~ 350kHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC-EP |
| 其它名称： | SC4525DSEDKR |
SC4525D
Applications Information (Cont.)
Including the voltage divider (R 4 and R 6 ), the control to
feedback transfer function is found and plotted in Figure
8 as the converter gain.
Since the converter gain has only one dominant pole at
low frequency, a simple Type-2 compensation network
is sufficient for voltage loop compensation. As shown in
3. Place the compensator zero, F Z , between 0% and
20% of the crossover frequency, F C .
4. Use the compensator pole, F P , to cancel the ESR zero,
F Z .
5. Then, the parameters of the compensation network
can be calculated by the following equations.
0 20
Figure 8, the voltage compensator has a low frequency
integrator pole, a zero at F Z , and a high frequency pole
at F P . The integrator is used to boost the gain at low
frequency. The zero is introduced to compensate the
excessive phase lag at the loop gain crossover due to the
integrator pole (-90deg) and the dominant pole (-90deg).
The high frequency pole nulls the ESR zero and attenuates
high frequency noise.
R 7 =
C 5 =
C 8 =
AC
g m
2 π F Z R 7
2 π F P R 7
where gm=0.3mA/V is the EA gain of the SC4525D.
Example: Determine the voltage compensator for an
350kHz, 2V to 3.3V/3A converter with 47uF ceramic
output capacitor.
Choose a loop gain crossover frequency of 35kHz, and
place voltage compensator zero and pole at F Z =7kHz
(20% of F C ), and F P = 677kHz. From the equation in step
2, the required compensator gain at F C is shown by the
following equation.
Figure 8 — Bode plots for voltage loop design
Therefore, the procedure of the voltage loop design for
the SC4525D can be summarized as:
. Plot the converter gain, i.e. control to feedback transfer
Then the compensator parameters are
10 20
0.3 x 10 ? 3
2 π x 7 x 10 x 7.4 x 10 3
function.
2. Select the open loop crossover frequency, F C ,
between 0% and 20% of the switching frequency. At
F C , find the required compensator gain, A C . In typical
applications with ceramic output capacitors, the ESR
zero is neglected and the required compensator gain
R 7 =
C 5 =
7
= 7.4 k
1
3
= 3.1 nF
A C = ? 20 x log ? ?
V FB ?
V O ? ?
C 8 =
= 32 pF
atF C canbeestimatedby
?
x
? G CA R S 2 π F C C O
x
?
1
2 π x 677 x 10 3 x 7.4 x 10 3
Select R 7 =7.32k, C 5 =3.3nF, and C 8 = 33pF for the design.
4
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