参数资料
| 型号： | SC4525DSETRT |
| 厂商： | Semtech |
| 文件页数： | 15/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 1 V ~ 16.74 V |
| 输入电压： | 3 V ~ 18 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 65kHz ~ 350kHz |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC-EP |
| 其它名称： | SC4525DSEDKR |
SC4525D
Applications Information (Cont.)
P SW =
x t S x V IN x I O x F SW
= D x V BST x O
P BST
Compensatorparametersforvarioustypicalapplications
are listed in Table 4. A MathCAD program is also available
upon request for detailed calculation of the compensator
parameters.
Thermal Considerations
For the power transistor inside the SC4525D, the
conduction loss P C , the switching loss P SW , and bootstrap
circuit loss P BST, can be estimated using the following.
P C = D x V CESAT x I O
2
I
40
where V BST is the BST supply voltage and t S is the equivalent
switching time of the NPN transistor (see Table 3).
Table 3 — Typical switching time
PCB Layout Considerations
In a step-down switching regulator, the input bypass
capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
operation, the size of the loop formed by these components
should be minimized. Since the power switch is already
integrated within the SC4525D, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.
V IN
V OUT
In addition, the quiescent current loss is
P Q = V IN x 2mA
The total power loss of the SC4525D is therefore
P TOTAL = P C + P SW + P BS T + P Q
The temperature rise of the SC4525D is the product of
the total power dissipation (previous equation) and q JA
(36 o C/W), which is the thermal impedance from junction
Z L
Figure 9 — Pulse Current Loop
Note: Heavy lines indicate the critical pulse current loop. The stray
inductance of this loop should be minimized.
to ambient for the SOIC-8 EDP package.
It is not recommended to operate the SC4525D above
25 o C junction temperature.
5
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