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参数资料
| 型号： | SCANPSC110FSCX |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28 |
| 封装： | 0.300 INCH, MS-013, SOIC-28 |
| 文件页数： | 5/25页 |
| 文件大小： | 269K |
| 代理商： | SCANPSC110FSCX |
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SCANPSC1
10F
Level 2 Protocol (Continued)
FIGURE 10. Local Scan Port Synchronization from Parked-RTI State
Register Descriptions
Instruction Register
The instruction shift register is an 8-bit register that is in
series with the scan chain whenever the TAP Controller of
the SCANPSC110F Bridge is in the Shift-IR state. Upon
exiting the Capture-IR state, the value “XXXXXX01” is cap-
tured into the instruction register, where “XXXXXX” repre-
sents the value on the S(0–5) inputs.
When the SCANPSC110F controller is in the Wait-For-
Address
state,
the
instruction
register
is
used
for
SCANPSC110F
selection
via
address
matching.
In
addressing individual SCANPSC110Fs, the chip’s address-
ing logic performs a comparison between a statically-con-
figured (hard-wired) value on that SCANPSC110F’s slot
inputs, and an address which is scanned into the chip’s
instruction
register.
Binary
address
codes
“000000”
through “111010” (“00” through “3A” Hex) are reserved for
addressing individual SCANPSC110Fs. Address “3B” Hex
is for Broadcast mode.
In doing multi-cast (group) addressing, a scanned-in
address is compared against the (previously scanned-in)
contents of a SCANPSC110F's Multi-Cast Group register.
Binary address codes “111110” through “111111” (“3A”
through “3F” Hex) are reserved for multi-cast addressing,
and should not be assigned as SCANPSC110F slot-input
values.
Boundary-Scan Register
The boundary-scan register is a “sample only” shift register
containing cells from the S(0–5) and OE inputs. The register
allows testing of circuitry external to the SCANPSC110F. It
permits the signals flowing between the system pins to be
sampled and examined without interfering with the opera-
tion of the on-chip system logic.
The scan chain is arranged as follows:
TDIB→OE →S5→S4→
S3 →S2→S1→S0→LSPN→TDOB
Bypass Register
The bypass register is a 1-bit register that operates as
specified in IEEE Std. 1149.1 once the SCANPSC110F has
been selected. The register provides a minimum length
serial path for the movement of test data between TDIB
and the LSPN. This path can be selected when no other
test data register needs to be accessed during a board-
level test operation. Use of the bypass register shortens
the serial access-path to test data registers located in other
components on a board-level test data path.
Multi-Cast Group Register
“Multi-cast” is a method of simultaneously communicating
with more than one selected SCANPSC110F.
The multi-cast group register (MCGR) is a 2-bit register
used to determine which multi-cast group a particular
SCANPSC110F is assigned to. Four addresses are
reserved
for
multi-cast
addressing.
When
a
SCANPSC110F is in the Wait-For-Address state and
receives a multi-cast address, and if that SCANPSC110F's
MCGR contains a matching value for that multi-cast
address, the SCANPSC110F becomes selected and is
ready to receive Level 2 Protocol (i.e., further instructions).
The MCGR is initialized to “00” upon entering the Test-
Logic-Reset state.
The following actions are used to perform multi-cast
addressing:
1. Assign all target SCANPSC110Fs to a multi-cast group
by writing each individual target SCANPSC110F's
MCGR with the same multi-cast group code (see Table
6). This configuration step must be done by individually
addressing each target SCANPSC110F, using that
chip's assigned slot value.
2. Scan out the multi-cast group address through the
TDIB input of all SCANPSC110Fs. Note that this occurs
in parallel, resulting in the selection of only those
SCANPSC110Fs whose MCGR was previously pro-
grammed with the matching multi-cast group code.
TABLE 6. Multi-Cast Group Register Addressing
MCGR
Hex Address
Binary Address
Bits 1, 0
00
3C
XX111100
01
3D
XX111101
10
3E
XX111110
11
3F
XX111111
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