参数资料
型号: SCF5250LAG100
厂商: Freescale Semiconductor
文件页数: 26/56页
文件大小: 0K
描述: IC MPU COLDFIRE 100MHZ 144-LQFP
标准包装: 60
系列: SCF52xx
核心处理器: Coldfire V2
芯体尺寸: 32-位
速度: 100MHz
连通性: EBI/EMI,I²C,IDE,MMC,SPI,UART/USART
外围设备: DMA,I²S,POR,串行音频,WDT
输入/输出数: 57
程序存储器类型: ROMless
RAM 容量: 128K x 8
电压 - 电源 (Vcc/Vdd): 1.08 V ~ 1.32 V
数据转换器: A/D 6x12b
振荡器型: 内部
工作温度: -20°C ~ 70°C
封装/外壳: 144-LQFP
包装: 托盘
SCF5250 Data Sheet: Technical Data, Rev. 1.3
32
Freescale Semiconductor
Figure 9 provides the I2C-bus and system clock timing diagram and Table 28 provides the I2C-bus output
timing parameters.
Figure 9. I2C and System Clock Timing Relationship
Table 28. I2C Output Bus Timings
Num
Characteristic
96 MHz
Units
Min
Max
M101
1 SCL and SDA are internally synchronized. This setup time must be met only if recognition on a particular clock is required.
SCL, SDA Valid to BCLK (input setup)
2
ns
M11
BCLK to SCL, SDA Invalid (input hold)
4.5
ns
M122
2 Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL
or SDA are driven low by the processor. The time required for SCL or SDA to reach a high level depends on external signal capacitance and
pull-up resistor values.
BCLK to SCL, SDA Low (output valid)
10
ns
M133
3 Since SCL and SDA are open-collector-type outputs, which the processor can only actively drive low, this specification applies only when SCL
or SDA are actively being driven or held low by the processor.
BCLK to SCL, SDA Invalid (output hold)
3
ns
BCLK
SCL, SDA IN
SCL, SDA OUT
M10
M11
M12
M13
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