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| 型号： | SCF5250LAG100 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 5/56页 |
| 文件大小： | 0K |
| 描述： | IC MPU COLDFIRE 100MHZ 144-LQFP |
| 标准包装： | 60 |
| 系列： | SCF52xx |
| 核心处理器： | Coldfire V2 |
| 芯体尺寸： | 32-位 |
| 速度： | 100MHz |
| 连通性： | EBI/EMI，I²C，IDE，MMC，SPI，UART/USART |
| 外围设备： | DMA，I²S，POR，串行音频，WDT |
| 输入/输出数： | 57 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 128K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.08 V ~ 1.32 V |
| 数据转换器： | A/D 6x12b |
| 振荡器型： | 内部 |
| 工作温度： | -20°C ~ 70°C |
| 封装/外壳： | 144-LQFP |
| 包装： | 托盘 |
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SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
13
3.2.2
Read-Write Control
This signal indicates during any bus cycle whether a read or write is in progress. A low is write cycle and
a high is a read cycle.
3.2.3
Output Enable
The OE signal is intended to be connected to the output enable of asynchronous memories connected to
chip selects. During bus read cycles, the ColdFire processor will drive OE low.
3.2.4
Data Bus
The data bus (D[31:16]) is bi-directional and non-multiplexed. Data is registered by the SCF5250 on the
rising clock edge. The data bus uses a default configuration if none of the chip-selects or DRAM bank
match the address decode. All 16 bits of the data bus are driven during writes, regardless of port width or
operand size.
3.2.5
Transfer Acknowledge
The TA/GPIO12 pin is the transfer acknowledge signal.
3.3
SDRAM Controller Signals
The following SDRAM signals provide a glueless interface to external SDRAM. An SDRAM width of 16
bits is supported and can access as much as 32MB of memory. ADRAMs are not supported.
Table 3. SDRAM Controller Signals
SDRAM Signal
Description
Synchronous DRAM row address strobe
The SDRAS/GPIO59 active low pin provides a seamless interface to the RAS input
on synchronous DRAM
Synchronous DRAM Column Address
Strobe
The SDCAS/GPIO39 active low pin provides a seamless interface to CAS input on
synchronous DRAM.
Synchronous DRAM Write
The SDWE/GPIO38 active-low pin is asserted to signify that a SDRAM write cycle
is underway. This pin outputs logic ‘1’ during read bus cycles.
Synchronous DRAM Chip Enable
The SD_CS0/GPIO60 active-low output signal is used during synchronous mode
to route directly to the chip select of a SDRAM device.
Synchronous DRAM UDQM and LQDM
signals
The DRAM byte enables UDMQ and LDQM are driven by the SDUDQM/GPO53
and SDLDQM/GPO52 byte enable outputs.
Synchronous DRAM clock
The DRAM clock is driven by the BCLK/GPIO40 signal
Synchronous DRAM Clock Enable
The BCLKE active high output signal is used during synchronous mode to route
directly to the SCKE signal of external SDRAMs. This signal provides the clock
enable to the SDRAM.
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