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| 型号： | SCF5250LAG100 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 45/56页 |
| 文件大小： | 0K |
| 描述： | IC MPU COLDFIRE 100MHZ 144-LQFP |
| 标准包装： | 60 |
| 系列： | SCF52xx |
| 核心处理器： | Coldfire V2 |
| 芯体尺寸： | 32-位 |
| 速度： | 100MHz |
| 连通性： | EBI/EMI，I²C，IDE，MMC，SPI，UART/USART |
| 外围设备： | DMA，I²S，POR，串行音频，WDT |
| 输入/输出数： | 57 |
| 程序存储器类型： | ROMless |
| RAM 容量： | 128K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.08 V ~ 1.32 V |
| 数据转换器： | A/D 6x12b |
| 振荡器型： | 内部 |
| 工作温度： | -20°C ~ 70°C |
| 封装/外壳： | 144-LQFP |
| 包装： | 托盘 |
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SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
5
The CD-ROM decoder performs following functions in hardware:
Sector sync recognition
Descrambling of sectors
Verification of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors
Third-layer error correction is not performed
The CD-ROM encoder performs following functions in hardware:
Sector sync recognition
Scrambling of sectors
Insertion of the CRC checksum for Mode 1, Mode 2 Form 1, and Mode 2 Form 2 sectors.
Third-layer error encoding needs to be done in software. This can use approximately 5–10 MHz of
performance for single-speed.
1.2.13
Dual UART Module
Two full-duplex UARTs with independent receive and transmit buffers are in this module. Data formats
can be 5, 6, 7, or 8 bits with even, odd, or no parity, and up to 2 stop bits in 1/16 increments. Four-byte
receive buffers and two-byte transmit buffers minimize CPU service calls. The Dual UART module also
provides several error-detection and maskable-interrupt capabilities. Modem support includes
request-to-send (RTS) and clear-to-send (CTS) lines.
The system clock provides the clocking function from a programmable prescaler. You can select full
duplex, auto-echo loopback, local loopback, and remote loopback modes. The programmable Dual UARTs
can interrupt the CPU on various normal or error-condition events.
1.2.14
Queued Serial Peripheral Interface QSPI
The QSPI module provides a serial peripheral interface with queued transfer capability. It supports up to
16 stacked transfers at a time, making CPU intervention between transfers unnecessary. Transfers of up to
15 Mbits/second are possible at a CPU clock of 120 MHz. The QSPI supports master mode operation only.
1.2.15
Timer Module
The timer module includes two general-purpose timers, each of which contains a free-running 16-bit timer.
Timer0 has an external pin TOUT0, which can be used in Output Compare mode. This mode triggers an
external signal or interrupts the CPU when the timer reaches a set value, and can also generate waveforms
on TOUT0.
The timer unit has an 8-bit prescaler that allows programming of the clock input frequency, which is
derived from the system clock. In addition to the ÷1 and ÷16 clock derived from the bus clock (CPU clock
/ 2), the programmable timer-output pins either generate an active-low pulse or toggle the outputs.
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