参数资料
型号: SE98ATL,147
厂商: NXP Semiconductors
文件页数: 33/43页
文件大小: 849K
描述: IC TEMP SENSOR DDR 3.6V 8-HXSON
标准包装: 1
功能: 温度监控系统(传感器)
传感器类型: 内部
感应温度: -40°C ~ 125°C
精确度: ±4°C(最小值)
拓扑: ADC(三角积分型),寄存器库
输出类型: I²C?/SMBus?
输出警报:
输出风扇:
电源电压: 1.7 V ~ 3.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-WFDFN 裸露焊盘
供应商设备封装: 8-WSON
包装: 标准包装
其它名称: 568-4780-6
SE98A_4
?NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04  25 November 2009
33 of 43
NXP Semiconductors
SE98A
DDR memory module temp sensor, 1.7 V to 3.6 V
 
[1]   Minimum clock frequency is 0 kHz if SMBus Time-out is disabled.
[2]   Delay from SDA STOP to SDA START.
[3]   A device must internally provide a hold time of at least 200 ns for SDA signal (referenced to the V
IH(min)
 of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
[4]   Delay from SCL HIGH-to-LOW transition to SDA edges.
[5]   Delay from SCL LOW-to-HIGH transition to restart SDA.
[6]   Delay from SDA START to first SCL HIGH-to-LOW transition.
 
Table 27.   SMBus AC characteristics
V
DD
= 1.7 V to 3.6 V; T
amb
= 40 ?/SPAN>C to +125 ?/SPAN>C; unless otherwise specified. These specifications are guaranteed by design.
The AC specifications fully meet or exceed SMBus 2.0 specifications, but allow the bus to interface with the I
2
C-bus from DC
to 400 kHz.
Symbol
Parameter
Conditions
Standard mode
Fast mode
Unit
Min
Max
Min
Max
f
SCL
SCL clock frequency
10
[1]
100
10
[1]
400    kHz
t
HIGH
HIGH period of the SCL clock  70 % to 70 %
4000
-
600
-
ns
t
LOW
LOW period of the SCL clock   30 % to 30 %
4700
-
1300
-
ns
t
to(SMBus)
SMBus time-out time
LOW period to reset
SMBus
25
35
25
35
ms
t
r
rise time of both SDA and
SCL signals
-
1000
20
300    ns
t
f
fall time of both SDA and SCL
signals
-
300
-
300    ns
t
SU;DAT
data set-up time
250
-
100
-
ns
t
h(i)(D)
data input hold time
[2]
[3]
0
-
0
-
ns
t
HD;DAT
data hold time
[4]
200
3450
200
900    ns
t
SU;STA
set-up time for a repeated
START condition
[5]
4700
-
600
-
ns
t
HD;STA
hold time (repeated) START
condition
30 % of SDA to
70 % of SCL
[6]
4000
-
600
-
ns
t
SU;STO
set-up time for STOP
condition
4000
-
600
-
ns
t
BUF
bus free time between a
STOP and START condition
[2]
4700
-
1300
-
ns
t
SP
pulse width of spikes that
must be suppressed by the
input filter
-
50
-
50
ns
t
VD;DAT
data valid time
from clock
200
-
200
-
ns
t
f(o)
output fall time
-
-
-
250    ns
t
POR
power-on reset pulse time
power supply falling
0.5
-
0.5
-
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