参数资料
型号: SED1225DAB
元件分类: 显示控制器
英文描述: 24 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC171
封装: DIE-171
文件页数: 21/39页
文件大小: 330K
代理商: SED1225DAB
5–28
EPSON
SED1225 Series
SIGNAL TIMING CHARACTERISTICS
(1) MPU bus write timing (80 series)
*1 The input signal rise and fall times (
tr, tf) are defined to be 25 nsec max (except for RES input).
*2 “
tCCL” is defined by the overlap time of XCS low level and XWR low level.
A0
XWR
D0 to D7
tAH8
tCYC8
tAC8
tAW8
tCCL
tCCH
tDS8
tDH8
XCS
VSS x 0.8 [V]
VSS x 0.2 [V]
tr
tf
(Ta = –30 to +85
°C, VSS = –3.3V to –2.7V)
Item
Signal
Symbol
Conditions
Min.
Max.
Unit
Address setup time
A0
tAW8
60
Address hold time
tAH8
30
ns
XCS setup time
XCS
tAC8
0—
System cycle time
tCYC8
All timing must be based on
1150
ns
Write "Lo" pulse width (XWR)
XWR
tCCL
20% and 80% of VSS.
100
ns
Write "Hi" pulse width (XWR)
tCCH
1000
ns
Data setup time
D0 to D7
tDS8
20
Data hold time
tDH8
20
ns
(Ta = –30 to +85
°C, VSS = –3.6V to –1.7V)
Item
Signal
Symbol
Conditions
Min.
Max.
Unit
Address setup time
A0
tAW8
60
Address hold time
tAH8
30
ns
XCS setup time
XCS
tAC8
0—
System cycle time
tCYC8
All timing must be based on
1850
ns
Write "Lo" pulse width (XWR)
XWR
tCCL
20% and 80% of VSS.
150
ns
Write "Hi" pulse width (XWR)
tCCH
1650
ns
Data setup time
D0 to D7
tDS8
50
Data hold time
tDH8
50
ns
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