参数资料
型号: SED1225DAB
元件分类: 显示控制器
英文描述: 24 X 60 DOTS DOT MAT LCD DRVR AND DSPL CTLR, UUC171
封装: DIE-171
文件页数: 22/39页
文件大小: 330K
代理商: SED1225DAB
EPSON
5–29
SED1225 Series
SED1225
Series
(2) MPU bus write timing (68 series)
*1 The input signal rise and fall times (
tr, tf) are defined to be 25 nsec max (except for RES input).
*2 “
tEWH” is defined by the overlap time of XCS low level and XWR low level.
tCYC6
tAW6
tEWL
tAC6
tEWH
tAH6
tDS6
tDH6
E
XCS
A0
D0 to D7
VSS x 0.8 [V]
VSS x 0.2 [V]
tr
tf
(Ta = –30 to +85
°C, VSS = –3.6V to –1.7V)
Item
Signal
Symbol
Conditions
Min.
Max.
Unit
Address setup time
A0
tAW6
60
Address hold time
tAH6
50
ns
XCS setup time
XCS
tAC6
0–
System cycle time
tCYC6
All timing must be based on
1850
ns
Enable "Lo" pulse width (XWR)
XWR
tEWL
20% and 80% of VSS.
1650
ns
Enable "Hi" pulse width (XWR)
tEWH
150
ns
Data setup time
D0 to D7
tDS6
20
Data hold time
tDH6
80
ns
(Ta = –30 to +85
°C, VSS = –3.3V to –2.7V)
Item
Signal
Symbol
Conditions
Min.
Max.
Unit
Address setup time
A0
tAW6
60
Address hold time
tAH6
30
ns
XCS setup time
XCS
tAC6
0–
System cycle time
tCYC6
All timing must be based on
1150
ns
Enable "Lo" pulse width (XWR)
XWR
tEWL
20% and 80% of VSS.
1000
ns
Enable "Hi" pulse width (XWR)
tEWH
100
ns
Data setup time
D0 to D7
tDS6
20
Data hold time
tDH6
50
ns
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