参数资料
型号: SI3050-E1-FT
厂商: Silicon Laboratories Inc
文件页数: 24/128页
文件大小: 0K
描述: IC VOICE DAA SYSTEM SIDE 20TSSOP
标准包装: 74
系列: *
Si3050 + Si3011/18/19
12
Rev. 1.5
Figure 4. PCM Highway Interface Timing Diagram (RXS = TXS = 1)
Table 8. Switching Characteristics—PCM Highway Serial Interface
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C, CL = 20 pF)
Parameter1
Symbol
Test
Conditions
Min
Typ
Max
Units
Cycle Time PCLK
tp
122
3906
ns
Valid PCLK Inputs
256
512
768
1.024
1.536
2.048
4.096
8.192
kHz
MHz
FSYNC Period2
tfp
—125
s
PCLK Duty Cycle
tdty
40
50
60
%
PCLK Jitter-Tolerance
tjitter
——
2
ns
FSYNC Jitter Tolerance
tjitter
±120
ns
Rise Time, PCLK
tr
25
ns
Fall Time, PCLK
tf
25
ns
Delay Time, PCLK Rise to DTX Active
td1
20
ns
Delay Time, PCLK Rise to DTX Transition
td2
20
ns
Delay Time, PCLK Rise to DTX Tri-State3
td3
20
ns
Setup Time, FSYNC Rise to PCLK Fall
tsu1
25
ns
Hold Time, PCLK Fall to FSYNC Fall
th1
20
ns
Setup Time, DRX Transition to PCLK Fall
tsu2
25
ns
Hold Time, PCLK Falling to DRX Transition
th2
20
ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH =VO – 0.4 V, VIL = 0.4 V, rise and fall
times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC must be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected.
t
su1
t
h1
t
p
t
su2
t
h2
t
d3
t
d2
t
d1
PCLK
FSYNC
DRX
DTX
t
fp
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