- 您现在的位置：买卖IC网 > PDF目录10910 > SI3050-E1-FT (Silicon Laboratories Inc)IC VOICE DAA SYSTEM SIDE 20TSSOP PDF资料下载
参数资料
| 型号： | SI3050-E1-FT |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 62/128页 |
| 文件大小： | 0K |
| 描述： | IC VOICE DAA SYSTEM SIDE 20TSSOP |
| 标准包装： | 74 |
| 系列： | * |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页当前第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页
Si3050 + Si3011/18/19
Rev. 1.5
39
5.29. Filter Selection
The Si3050 supports additional filter selections for the
receive and transmit signals as defined in Tables 10 and
11. The IIRE bit (Register 16, bit 4) selects between the
IIR and FIR filters. The IIR filter provides a shorter, but
non-linear, group delay alternative to the default FIR
filter, and only operates with an 8 kHz sample rate. The
FILT
bit
(Register 31, bit 1)
selects
a
–3 dB
low
frequency pole of 5 Hz when cleared and a –3 dB low
frequency pole of 200 Hz (per EIA/TIA 464) when set.
The FILT bit affects the receive path only.
5.30. Clock Generation
The Si3050 generates the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256kHz, 512kHz, 768kHz,
1.024 MHz,
1.53 MHz,
2.048 MHz,
4.09 MHz,
or
8.192 MHz. The ratio of the PCLK rate to the FSYNC
rate is determined internally by the DAA and is
transferred into internal registers after a reset. These
internal registers are not accessible through register
reads or writes. Figure 29 shows the operation of the
Si3050 clock circuitry.
The PLL clock synthesizer settles quickly after powerup.
However, the settling time depends on the PCLK
frequency and it can be approximately predicted by the
following equation:
Tsettle =64/FPCLK
For all valid PCLK frequencies listed above, the default
line sample rate is 8 kHz. This sample rate can be
increased
to
16 kHz
by
setting
the
HSSM
bit
(Register 7, bit 3). Regardless of the sample rate
frequency, the serial data communication rate of the
PCM and GCI highways remains 8 kHz. When the
16 kHz sample rate is selected, additional timeslots in
the PCM or GCI highway are used to transfer the
additional data.
5.31. Communication Interface Mode
Selection
The Si3050 supports two communication interface
protocols:
PCM/SPI mode where data and control information
transmission/reception occurs across separate
buses (PCM highway for data, and SPI port for
control).
GCI mode where data and control information is
multiplexed and transmission/reception occurs
across the GCI highway bus.
A pin-strapping method (specifically, the state of SCLK
on power-up [reset]) is used to select between the two
specify how to select a communication mode, and how
the various pins are used in each mode.
When operating in PCM/SPI mode, the GCI control
register should not be written (i.e., Register 42 must
each remain set at 0000_0000 when using the PCM/
SPI highway mode). Similarly, when operating in GCI
highway mode the PCM registers should not be written
(i.e., Registers 33–37 must remain set to 0000_0000
when using the GCI highway mode).
Figure 29. PLL Clock Synthesizer
PFD
VCO
2
16.384 MHz
DIV M
PCLK
Internal PLL
Register
2
N
相关PDF资料 |
PDF描述 |
|---|---|
| PIC16C54/JW | IC MCU EPROM 512X12 18CDIP |
| SI3056-D-FS | IC SYSTEM-SIDE DAA 16SOIC |
| PIC16C71/JW | IC MCU EPROM 1KX14 A/D 18CDIP |
| SI3018-F-FS-R | IC ISOMODEM LINE-SIDE DAA 16SOIC |
| VE-2N3-IX-F4 | CONVERTER MOD DC/DC 24V 75W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| SI3050-E1-FTR | 制造商:Silicon Laboratories Inc 功能描述:Voice DAA Chipset 20-Pin TSSOP T/R 制造商:Silicon Laboratories Inc 功能描述:SI3050 VOICE DAA SYSTEM-SIDE - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:3.3VH PROGRAMMABLE VOICE DAA SYSTM-SIDE 制造商:Silicon Laboratories Inc 功能描述:IC VOICE DAA SYSTEM SIDE 20TSSOP 制造商:Silicon Laboratories Inc 功能描述:Si3050 Voice DAA System-Side |
| Si3050-E1-GM | 功能描述:电信线路管理 IC System-side Voice DAA RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI3050-E1-GMR | 制造商:Silicon Laboratories Inc 功能描述:SI3050 VOICE DAA SYSTEM-SIDE - LEAD-FREE - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC VOICE DAA SYSTEM SIDE 24QFN 制造商:Silicon Laboratories Inc 功能描述:Si3050 Voice DAA System-Side |
| Si3050-E1-GT | 功能描述:电信线路管理 IC System-side Voice DAA RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI3050-E1-GTR | 制造商:Silicon Laboratories Inc 功能描述:SI3050 VOICE DAA SYSTEM-SIDE - Tape and Reel 制造商:Silicon Laboratories Inc 功能描述:IC VOICE DAA SYSTEM SIDE 24QFN 制造商:Silicon Laboratories Inc 功能描述:Si3050 Voice DAA System-Side |
发布紧急采购，3分钟左右您将得到回复。