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参数资料
型号： SI3050-E1-FT
厂商： Silicon Laboratories Inc
文件页数： 86/128页
文件大小： 0K
描述： IC VOICE DAA SYSTEM SIDE 20TSSOP
标准包装： 74
系列： *
Si3050 + Si3011/18/19
60
Rev. 1.5
CIR1: OH
Data that is received must be consistent and match for at least two consecutive frames to be considered valid.
When a new command or status is communicated via the C/I bits, the data must be sent for at least two
consecutive frames to be recognized by the Si3050. The following steps describe the protocol of how C/I bits are
stored, detected, and validated. This is illustrated in Figure 49.
1. The current state of the C/I bits are stored in a primary register P. If the received C/I bits are identical to this
current state, no action is taken.
2. Upon receipt of an SC channel with C/I bits that differ from the current state, these new C/I bits are immediately
latched into a secondary register S.
3. The C/I bits in the SC channel received in the frame immediately after the SC channel just stored in S are
compared with the C/I bits in the S register.
a. If the C/I bits in these two channels are identical, then the C/I bits in the S register are loaded into the P
register and are considered a valid change of C/I bits. The Si3050 then responds accordingly to the changed
C/I bits.
b. If a set of C/I bits is latched into the S register and the subsequent set of C/I bits received does not match
either the S or P registers, then the newly received set of C/I bits are latched into the S register. This
continues to occur as long as the subsequent set of C/I bits received differs from the C/I bits in the S and
Pregisters.
c. If the C/I bits in the SC channel received immediately after the SC channel just stored in S do not match the
C/I bits stored in S, but DO match the C/I bits stored in P, then the single set of C/I bits stored in the S latch
are invalidated, and the current state of the C/I bits in P remains unchanged.
Figure 49. Protocol for Receiving C/I Bits in the Si3050
Receive New
CI Code
Store in S
Receive New
C/I Code
= P?
= S?
Load C/I Register
With New C/I Bits
Yes
No
Yes
No
P: C/I Primary Register Contents
S: C/I Secondary Register Contents
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