参数资料
型号: SI4505DY-T1-E3
厂商: Vishay Siliconix
文件页数: 2/12页
文件大小: 0K
描述: MOSFET N/P-CH 8-SOIC
标准包装: 2,500
系列: TrenchFET®
FET 型: N 和 P 沟道
FET 特点: 逻辑电平门
漏极至源极电压(Vdss): 30V,8V
电流 - 连续漏极(Id) @ 25° C: 6A,3.8A
开态Rds(最大)@ Id, Vgs @ 25° C: 18 毫欧 @ 7.8A,10V
Id 时的 Vgs(th)(最大): 1.8V @ 250µA
闸电荷(Qg) @ Vgs: 20nC @ 5V
功率 - 最大: 1.2W
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
Si4505DY
Vishay Siliconix
SPECIFICATIONS T J = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ. a
Max.
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
V GS(th)
I GSS
V DS = V GS , I D = 250 μA
V DS = V GS , I D = - 250 μA
V DS = 0 V, V GS = ± 20 V
V DS = 0 V, V GS = ± 8 V
N-Ch
P-Ch
N-Ch
P-Ch
0.8
- 0.45
1.8
- 1.0
± 100
± 100
V
nA
V DS = 30 V, V GS = 0 V
N-Ch
1
Zero Gate Voltage Drain Current
I DSS
V DS = - 8 V, V GS = 0 V
V DS = 30 V, V GS = 0 V, T J = 55 °C
P-Ch
N-Ch
-1
5
μA
V DS = - 8 V, V GS = 0 V, T J = 55 °C
P-Ch
-5
On-State Drain Current b
I D(on)
V DS = 5 V, V GS = 10 V
V DS = - 5 V, V GS = - 4.5 V
V GS = 10 V, I D = 7.8 A
N-Ch
P-Ch
N-Ch
20
- 20
0.015
0.018
A
Drain-Source On-State Resistance b
R DS(on)
V GS = - 4.5 V, I D = - 5.0 A
V GS = 4.5 V, I D = 6.4 A
P-Ch
N-Ch
0.030
0.022
0.042
0.027
Ω
V GS = - 2.5 V, I D = - 4.0 A
P-Ch
0.048
0.060
Forward Transconductance b
g fs
V DS = 15 V, I D = 7.8 A
V DS = - 15 V, I D = - 5.0 A
N-Ch
P-Ch
18
12
S
Diode Forward Voltage b
V SD
I S = 1.8 A, V GS = 0 V
I S = - 1.8 A, V GS = 0 V
N-Ch
P-Ch
0.73
- 0.75
1.1
- 1.1
V
Dynamic a
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q g
Q gs
Q gd
t d(on)
t r
t d(off)
t f
t rr
N-Channel
V DS = 15 V, V GS = 5 V, I D = 7.8 A
P-Channel
V DS = - 4 V, V GS = - 5 V, I D = - 5.0 A
N-Channel
V DD = 15 V, R L = 15 Ω
I D ? 1 A, V GEN = 10 V, R G = 6 Ω
P-Channel
V DD = - 4 V, R L = 4 Ω
I D ? - 1 A, V GEN = - 4.5 V, R g = 6 Ω
I F = 1.8 A, dI/dt = 100 A/μs
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
11.5
13.5
3
2.2
4
3
15
21
8
45
35
60
10
55
30
50
20
20
25
40
15
70
55
100
20
85
60
100
nC
ns
Notes:
a. Guaranteed by design, not subject to production testing.
b. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
www.vishay.com
2
Document Number: 71826
S09-0868-Rev. C, 18-May-09
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