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| 型号： | SI4562DY-T1-E3 |
| 厂商： | Vishay Siliconix |
| 文件页数： | 2/10页 |
| 文件大小： | 0K |
| 描述： | MOSFET N/P-CH 20V 8-SOIC |
| 标准包装： | 2,500 |
| 系列： | TrenchFET® |
| FET 型： | N 和 P 沟道 |
| FET 特点： | 逻辑电平门 |
| 漏极至源极电压(Vdss)： | 20V |
| 开态Rds（最大）@ Id, Vgs @ 25° C： | 25 毫欧 @ 7.1A，4.5V |
| Id 时的 Vgs(th)（最大）： | 1.6V @ 250µA |
| 闸电荷(Qg) @ Vgs： | 50nC @ 4.5V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
Si4562DY
Vishay Siliconix
SPECIFICATIONS T J = 25 °C, unless otherwise noted
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Static
Gate Threshold Voltage
Gate-Body Leakage
V GS(th)
I GSS
V DS = V GS , I D = 250 μA
V DS = V GS , I D = - 250 μA
V DS = 0 V, V GS = ± 12 V
N-Ch
P-Ch
N-Ch
P-Ch
0.6
- 0.6
1.6
- 1.6
± 100
± 100
V
nA
V DS = 20 V, V GS = 0 V
N-Ch
1
Zero Gate Voltage Drain Current
I DSS
V DS = - 20 V, V GS = 0 V
V DS = 20 V, V GS = 0 V, T J = 55 °C
P-Ch
N-Ch
-1
5
μA
V DS = - 20 V, V GS = 0 V, T J = 55 °C
P-Ch
-5
On-State Drain Current b
I D(on)
V DS ≥ 5 V, V GS = 4.5 V
V DS ≤ - 5 V, V GS = - 4.5 V
V GS = 4.5 V, I D = 7.1 A
N-Ch
P-Ch
N-Ch
20
- 20
0.019
0.025
A
Drain-Source On-State Resistance b
R DS(on)
V GS = - 4.5 V, I D = - 6.2 A
V GS = 2.5 V, I D = 6.0 A
P-Ch
N-Ch
0.027
0.025
0.033
0.035
Ω
V GS = - 2.5 V, I D = - 5.0 A
P-Ch
0.040
0.050
Forward Transconductance b
Diode Forward Voltage b
g fs
V SD
V DS = 10 V, I D = 7.1 A
V DS = - 10 V, I D = - 6.2 A
I S = 1.7 A, V GS = 0 V
I S = - 1.7 A, V GS = 0 V
N-Ch
P-Ch
N-Ch
P-Ch
27
20
1.2
- 1.2
S
V
Dynamic b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Sorce-Drain Reverse Recovery Tme
Q g
Q gs
Q gd
t d(on)
t r
t d(off)
t f
t rr
N-Channel
V DS = 10 V, V GS = 4.5 V, I D = 7.1 A
P-Channel
V DS = - 10 V, V GS = - 4.5 V, I D = - 6.2 A
N-Channel
V DD = 10 V, R L = 10 Ω
I D ? 1 A, V GEN = 4.5 V, R g = 6 Ω
P-Channel
V DD = - 10 V, R L = 10 Ω
I D ? - 1 A, V GEN = - 4.5 V, R g = 6 Ω
I F = 1.7 A, dI/dt = 100 A/μs
I F = - 1.7 A, dI/dt = 100 A/μs
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
25
22
6.5
7
4
3.5
40
27
40
32
90
95
40
45
40
40
50
35
60
50
60
50
150
150
60
70
80
80
nC
ns
Notes:
a. For design aid only; not subject to production testing.
b. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2 %.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
www.vishay.com
2
Document Number: 70717
S09-0867-Rev. C, 18-May-09
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