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| 型号： | SI5100-G-BC |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 21/40页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SERIAL/DESERIAL 195CBGA |
| 标准包装： | 126 |
| 系列： | SiPHY™ |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | SONET/SDH |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 195-BBGA |
| 供应商设备封装： | 195-BGA（15x15） |
| 包装： | 托盘 |
| 其它名称： | 336-1308 SI5100-G-BC-ND |
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Si5100
28
Rev. 1.5
H4
REFRATE
I
LVTTL
Reference Clock Rate Select.
The REFRATE input sets the frequency for the
REFCLK input. When REFRATE is set high, the
REFCLK frequency is 1/16th the serial data rate
(nominally 155 MHz). When REFRATE is set
low, the REFCLK frequency is 1/32nd the serial
data rate (nominally 78 MHz).
The REFRATE input has no effect when the
REFSEL input is set low.
Note: This input has an internal pullup.
L12
REFSEL
I
LVTTL
Reference Clock Selection.
This input selects the reference clock source to
be used by the Si5100 transmitter and receiver.
The reference clock sets the operating fre-
quency of the Si5100 transmit CMU, which is
used to generate the high-speed transmit clock
TXCLKOUT. The reference clock is also used by
the Si5100 receiver CDR to center the PLL dur-
ing lock acquisition, and as a reference for deter-
mination of the receiver lock status.
When REFSEL = 0, the low-speed data input
clock, TXCLK16IN, is used as the reference
clock. When REFSEL = 1, the reference clock
provided on REFCLK is used.
Note: This input has an internal pullup.
G4
RESET
I
LVTTL
Device Reset.
Forcing this input low for a at least 1
s causes a
device reset. For normal operation, this pin
should be held high.
Note: This input has an internal pullup.
C6–7, D3, K4,
L4, M8, M11
RSVD_GND
Reserved Tie to Ground.
Must be connected directly to GND for proper
operation.
C10
RXAMPMON
O
Analog
Receiver Amplitude Monitor.
The RXAMPMON output provides an analog
output signal that is proportional to the input
signal
amplitude.
See
Equation 1 for
the
relationship between the RXAMPMON output
and RXDIN input. This signal is active when
SLICEMODE is asserted.
A2
A3
RXCLK1+
RXCLK1–
OLVDS
Differential Receiver Clock Output 1.
The clock recovered from the signal present on
RXDIN is divided down to the parallel output
word rate and output on RXCLK1. In the
absence of data, a stable clock on RXCLK1 can
be maintained by asserting LTR.
Pin Number(s)
Name
I/O
Signal Level
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| Si5100-H-BL | 功能描述:电信线路管理 IC OC-48 STM-16 SONET SDH Trnscvr 1:16 RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| Si5100-H-GL | 功能描述:电信线路管理 IC OC-48 STM-16 SONET SDH Trnscvr 1:16 RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI-51010-F | 制造商:Bel Fuse 功能描述:- Trays |
| SI-51011-F | 制造商:BEL 制造商全称:Bel Fuse Inc. 功能描述:SI-51011-F |
| SI-51012-F | 制造商:BEL 制造商全称:Bel Fuse Inc. 功能描述:SI-51012-F |
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