参数资料
型号: SI5100-G-BC
厂商: Silicon Laboratories Inc
文件页数: 22/40页
文件大小: 0K
描述: IC TXRX SERIAL/DESERIAL 195CBGA
标准包装: 126
系列: SiPHY™
类型: 收发器
驱动器/接收器数: 1/1
规程: SONET/SDH
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
封装/外壳: 195-BBGA
供应商设备封装: 195-BGA(15x15)
包装: 托盘
其它名称: 336-1308
SI5100-G-BC-ND
Si5100
Rev. 1.5
29
B2
B3
RXCLK2+
RXCLK2–
OLVDS
Differential Receiver Clock Output 2.
An auxiliary output clock is provided on this pin
that is equivalent to, or a submultiple of, the out-
put word rate. The divide factor used in generat-
ing RXCLK2 is set via RXCLK2DIV.
C12
RXCLK2DIV
I
LVTTL
RXCLK2 Clock Divider Select.
This input selects the divide factor used to gen-
erate the RXCLK2 output. When this input is
driven high, RXCLK2 is equal to the output word
rate on RXDOUT. When driven low, RXCLK2 is
1/4th the output word rate.
Note: This input has an internal pullup.
F4
RXCLK1DSBL
I
LVTTL
RXCLK1 Disable.
Setting this input low disables the RXCLK1 output.
This is used to save power in applications that do not
require the primary output clock.
Note: This input has an internal pullup.
C8
RXCLK2DSBL
I
LVTTL
RXCLK2 Disable.
Setting this input low disables the RXCLK2 out-
put. This saves power in applications that do not
require an auxiliary clock.
Note: This input has an internal pullup.
D1
E1
RXDIN+
RXDIN–
I
High-Speed
Differential
Differential Receive Data Input.
The receive clock and data signals RXCLK1,
RXCLK2, and RXDOUT[15:0] are recovered
from the high-speed data signal present on
these pins.
Pin Number(s)
Name
I/O
Signal Level
Description
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