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| 型号： | SI5110-H-BL |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 10/36页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99-PBGA |
| 标准包装： | 168 |
| 系列： | SiPHY™ |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | SONET/SDH |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 99-LBGA |
| 供应商设备封装： | 99-BGA（11x11） |
| 包装： | 托盘 |
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Si5110
18
Rev. 1.5
5.6. Auxiliary Clock Output
To
support
the
widest
range
of
system
timing
configurations, The Si5110 provides a primary clock
output on RXCLK1 and a secondary clock output
(RXCLK2). The RXCLK2 output can be configured to
provide a clock that is 1/4th or 1/16th the frequency of
the high-speed recovered clock. The divide ratio which
determines the RXCLK2 output frequency is selected by
RXCLK2DIV.
5.7. Receive Data Squelch
During some system error conditions, such as LOS, it
may be desirable to force the receive data output to
zero in order to avoid propagation of erroneous data
into the downstream electronics. The Si5110 provides a
data squelching control input, RXSQLCH, for this
purpose.
When the RXSQLCH input is low, the data outputs
RXDOUT[3:0]
are
forced
to
a
zero
state.
The
RXSQLCH input is ignored when the device is operating
in Diagnostic Loopback mode (DLBK = 0).
6. Transmitter
The transmitter consists of a low jitter clock multiplier
unit (CMU) with a 4:1 serializer. The CMU uses a
phase-locked loop (PLL) architecture based on Silicon
Laboratories’
proprietary
DSPLL
technology.
This
technology generates ultra-low jitter clock and data
outputs
that
provide
significant
margin
to
the
SONET/SDH specifications. The DSPLL architecture
also utilizes a digitally implemented loop filter that
eliminates the need for external loop filter components.
As a result, sensitive noise coupling nodes that typically
degrade
jitter
performance
in
crowded
PCB
environments are removed.
The DSPLL also reduces the complexity and relaxes
the performance requirements for reference clock
distribution circuitry for OC-48/STM-16 optical port
cards. The DSPLL provides selectable wideband and
narrowband loop filter settings that allow the jitter
attenuation characteristics of the CMU to be optimized
for the jitter content of the supplied reference clock. This
allows the CMU to operate with reference clocks that
have relatively high jitter content.
Unlike traditional analog PLL implementations, the loop
filter bandwidth of the Si5110 transmitter CMU is
controlled by a digital filter inside the DSPLL circuit
allowing the bandwidth to be changed without changing
any external component values.
6.1. DSPLL Clock Multiplier Unit
The Si5110’s clock multiplier unit (CMU) uses Silicon
Laboratories proprietary DSPLL technology to achieve
optimal jitter performance. The DSPLL implementation
utilizes a digital signal processing (DSP) algorithm to
replace the loop filter commonly found in analog PLL
designs. This algorithm processes the phase detector
error term and generates a digital control value to adjust
the frequency of the voltage-controlled oscillator (VCO).
The DSPLL implementation requires no external loop
filter components. Eliminating sensitive noise entry
points
makes
the
DSPLL
implementation
less
susceptible to board-level noise sources and makes
SONET/SDH jitter compliance easier to attain in the
application.
The transmit CMU multiplies the frequency of the
selected reference clock up to the serial transmit data
rate. The TXLOL output signal provides an indication of
the transmit CMU lock status. When the CMU has
achieved lock with the selected reference, the TXLOL
output is deasserted (driven high). The TXLOL signal
will be asserted, indicating a transmit CMU loss-of-lock
condition, when a valid clock signal is not detected on
the selected reference clock input. The TXLOL signal
will also be asserted during the transmit CMU frequency
calibration. Calibration is performed automatically when
the Si5110 is powered on, when a valid clock signal is
detected on the selected reference clock input following
a period when no valid clock was present, or when the
frequency of the selected reference clock is outside of
the transmit CMU’s PLL lock range or after RESET is
deasserted.
6.1.1. Programmable Loop Filter Bandwidth
The digitally implemented loop filter allows for four
transmit CMU loop bandwidth settings that provide
wideband or narrowband jitter transfer characteristics.
The filter bandwidth is selected via the BWSEL[1:0]
control inputs. The loop bandwidth choices are listed in
Unlike
traditional
PLL
implementations,
changing the loop filter bandwidth of the Si5110 is
accomplished without the need to change external
component values.
Lower loop bandwidth settings (Narrowband operation)
make the Si5110 more tolerant to jitter on the reference
clock source. As a result, circuitry used to generate and
distribute the physical layer reference clocks can be
simplified
without
compromising
margin
to
the
SONET/SDH jitter specifications.
Higher loop bandwidth settings (Wideband operation)
are useful in applications where the reference clock is
provided by a low jitter source like the Si5364 Clock
Synchronization
IC
or
Si5320
Precision
Clock
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相关代理商/技术参数 |
参数描述 |
|---|---|
| Si5110-H-GL | 功能描述:电信线路管理 IC OC-48 STM-16 SONET SDH Trnscvr 1:16 RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI5110-H-XL4 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI5110-H-ZL3 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI511BBA200M000BAGR | 制造商:Silicon Laboratories Inc 功能描述:SLLSI511BBA200M000BAGR OSC (200MHZ) |
| SI51210 | 制造商:SILABS 制造商全称:SILABS 功能描述:TWO OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR |
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