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| 型号： | SI5110-H-BL |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 21/36页 |
| 文件大小： | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 99-PBGA |
| 标准包装： | 168 |
| 系列： | SiPHY™ |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | SONET/SDH |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 99-LBGA |
| 供应商设备封装： | 99-BGA（11x11） |
| 包装： | 托盘 |
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Si5110
28
Rev. 1.5
A8
A7
RXCLK2+,
RXCLK2–
OLVDS
Differential Receiver Clock Output 2.
An auxiliary output clock is provided on this pin that is
equivalent to, or a submultiple of, the output word rate.
The divide factor used in generating RXCLK2 is set
via RXCLK2DIV.
C8
RXCLK2DIV
I
LVTTL
RXCLK2 Clock Divider Select.
This input selects the divide factor used to generate
the RXCLK2 output. When this input is driven high,
RXCLK2 is equal to the output word rate on RXDOUT.
When driven low, RXCLK2 is 1/4th the output word
rate.
Note: This input has an internal pullup.
D3
RXCLK1DSBL
I
LVTTL
RXCLK1 Disable.
Setting this input low disables the RXCLK1 output.
This is used to save power in applications that do not
require the primary output clock.
Note: This input has an internal pullup.
C7
RXCLK2DSBL
I
LVTTL
RXCLK2 Disable.
Setting this input low disables the RXCLK2 output.
This saves power in applications that do not require
an auxiliary clock.
Note: This input has an internal pullup.
B1, C1
RXDIN+,
RXDIN–
I
High-Speed
Differential
Differential Receive Data Input.
The receive clock and data signals RXCLK1,
RXCLK2, and RXDOUT[3:0] are recovered from the
high-speed data signal present on these pins.
C9
D9
C10
D10
A9
B9
A10
B10
RXDOUT3+
RXDOUT3–
RXDOUT2+
RXDOUT2–
RXDOUT1+
RXDOUT1–
RXDOUT0+
RXDOUT0–
OLVDS
Differential Parallel Receive Data Output.
The data recovered from the signal present on RXDIN
is demultiplexed and output as a 4-bit parallel word via
RXDOUT[3:0]. The bit order for demultiplexing is
selected by the RXMSBSEL input. The RXDOUT[3:0]
outputs are aligned to the rising edge of RXCLK1.
C3
RXLOL
O
LVTTL
Receiver Loss-of-Lock.
This output is asserted (driven low) when the recov-
ered clock frequency deviates from the reference
clock by the amount specified in Table 5 on page 9.
Pin
Number(s)
Name
I/O
Signal Level
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| Si5110-H-GL | 功能描述:电信线路管理 IC OC-48 STM-16 SONET SDH Trnscvr 1:16 RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| SI5110-H-XL4 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI5110-H-ZL3 | 制造商:Silicon Laboratories Inc 功能描述:OC-48 TRANSCEIVER, LIA, CDR, 4:1 MUX, 1:4 DEMUX - Rail/Tube |
| SI511BBA200M000BAGR | 制造商:Silicon Laboratories Inc 功能描述:SLLSI511BBA200M000BAGR OSC (200MHZ) |
| SI51210 | 制造商:SILABS 制造商全称:SILABS 功能描述:TWO OUTPUTS FACTORY PROGRAMMABLE CLOCK GENERATOR |
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